Hi Guys,
I am applying the patch below to remove the duplicate register classes
from the FRV backend. This was causing problems with the IRA
initialization code.
Cheers
Nick
gcc/ChangeLog
2011-04-27 Nick Clifton <ni...@redhat.com>
* config/frv/frv.h (enum reg_class): Delete EVEN_ACC_REGS,
ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(EVEN_ACC_REGS): New macro. Alias for QUAD_ACC_REGS.
(ACC_REGS): New macro. Alias for QUAD_ACC_REGS.
(FEVEN_REGS): New macro. Alias for QUAD_ACC_REGS.
(FPR_REGS): New macro. Alias for QUAD_ACC_REGS.
(EVEN_REGS): New macro. Alias for QUAD_REGS.
* config/frv/frv.c (frv_secondary_reload_class): Remove use of
duplicate register classes.
(frv_class_likely_spileld_p): Likewise.
(frv_register_move_cost): Likewise.
Index: gcc/config/frv/frv.h
===================================================================
--- gcc/config/frv/frv.h (revision 173012)
+++ gcc/config/frv/frv.h (working copy)
@@ -864,14 +864,9 @@
FDPIC_CALL_REGS,
SPR_REGS,
QUAD_ACC_REGS,
- EVEN_ACC_REGS,
- ACC_REGS,
ACCG_REGS,
QUAD_FPR_REGS,
- FEVEN_REGS,
- FPR_REGS,
QUAD_REGS,
- EVEN_REGS,
GPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
@@ -904,14 +899,9 @@
"FDPIC_CALL_REGS", \
"SPR_REGS", \
"QUAD_ACC_REGS", \
- "EVEN_ACC_REGS", \
- "ACC_REGS", \
"ACCG_REGS",
\
"QUAD_FPR_REGS", \
- "FEVEN_REGS", \
- "FPR_REGS", \
"QUAD_REGS",
\
- "EVEN_REGS",
\
"GPR_REGS", \
"ALL_REGS" \
}
@@ -945,18 +935,19 @@
{ 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /*
FDPIC_CALL_REGS */\
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /*
SPR_REGS */\
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC
*/\
- { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* EVEN_ACC
*/\
- { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* ACC_REGS
*/\
{ 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /*
ACCG_REGS*/\
{ 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR
*/\
- { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /*
FEVEN_REG*/\
- { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FPR_REGS
*/\
{ 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /*
QUAD_REGS*/\
- { 0xfffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /*
EVEN_REGS*/\
{ 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS
*/\
{ 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /*
ALL_REGS */\
}
+#define EVEN_ACC_REGS QUAD_ACC_REGS
+#define ACC_REGS QUAD_ACC_REGS
+#define FEVEN_REGS QUAD_FPR_REGS
+#define FPR_REGS QUAD_FPR_REGS
+#define EVEN_REGS QUAD_REGS
+
/* A C expression whose value is a register class containing hard register
REGNO. In general there is more than one such class; choose a class which
is "minimal", meaning that no smaller class also contains the register. */
Index: gcc/config/frv/frv.c
===================================================================
--- gcc/config/frv/frv.c (revision 173012)
+++ gcc/config/frv/frv.c (working copy)
@@ -6371,7 +6371,6 @@
/* Accumulators/Accumulator guard registers need to go through floating
point registers. */
case QUAD_REGS:
- case EVEN_REGS:
case GPR_REGS:
ret = NO_REGS;
if (x && GET_CODE (x) == REG)
@@ -6385,8 +6384,6 @@
/* Nonzero constants should be loaded into an FPR through a GPR. */
case QUAD_FPR_REGS:
- case FEVEN_REGS:
- case FPR_REGS:
if (x && CONSTANT_P (x) && !ZERO_P (x))
ret = GPR_REGS;
else
@@ -6406,8 +6403,6 @@
break;
/* The accumulators need fpr registers. */
- case ACC_REGS:
- case EVEN_ACC_REGS:
case QUAD_ACC_REGS:
case ACCG_REGS:
ret = FPR_REGS;
@@ -6481,8 +6476,6 @@
case LR_REG:
case SPR_REGS:
case QUAD_ACC_REGS:
- case EVEN_ACC_REGS:
- case ACC_REGS:
case ACCG_REGS:
return true;
}
@@ -6842,19 +6835,16 @@
break;
case QUAD_REGS:
- case EVEN_REGS:
case GPR_REGS:
switch (to)
{
default:
break;
- case QUAD_REGS:
- case EVEN_REGS:
+ case QUAD_REGS:
case GPR_REGS:
return LOW_COST;
- case FEVEN_REGS:
case FPR_REGS:
return LOW_COST;
@@ -6864,24 +6854,19 @@
return LOW_COST;
}
- case FEVEN_REGS:
- case FPR_REGS:
+ case QUAD_FPR_REGS:
switch (to)
{
default:
break;
case QUAD_REGS:
- case EVEN_REGS:
case GPR_REGS:
- case ACC_REGS:
- case EVEN_ACC_REGS:
case QUAD_ACC_REGS:
case ACCG_REGS:
return MEDIUM_COST;
- case FEVEN_REGS:
- case FPR_REGS:
+ case QUAD_FPR_REGS:
return LOW_COST;
}
@@ -6894,13 +6879,10 @@
break;
case QUAD_REGS:
- case EVEN_REGS:
case GPR_REGS:
return MEDIUM_COST;
}
- case ACC_REGS:
- case EVEN_ACC_REGS:
case QUAD_ACC_REGS:
case ACCG_REGS:
switch (to)
@@ -6908,8 +6890,7 @@
default:
break;
- case FEVEN_REGS:
- case FPR_REGS:
+ case QUAD_FPR_REGS:
return MEDIUM_COST;
}
