The following patch is to solve the PR. The reason for the problem is
described on
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48380
I also found some problem with function fix_reg_equiv_init (it calls
grow_reg_equivs) whose code is never executed anymore because
grow_reg_equivs is called before fix_reg_equiv_init now. I fixed that,
please see all difference for file ira.c
Ok to commit if the patch is successfully bootstrapped on x86_64 and x86
with H.J.'s tester parameters (unfortunately right now I can not check
my patch because a recent patch resulted in a bootstrap failure).
2011-04-01 Vladimir Makarov <vmaka...@redhat.com>
PR target/48380
* ira.c (ira): Call grow_reg_equivs when fix_reg_equiv_init is
not called.
* ira-emit.c (emit_move_list): Update reg equiv init insn list.
Index: ira.c
===================================================================
--- ira.c (revision 171852)
+++ ira.c (working copy)
@@ -3657,8 +3657,6 @@ ira (FILE *f)
if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
df_analyze ();
- grow_reg_equivs ();
-
if (max_regno != max_regno_before_ira)
{
regstat_free_n_sets_and_refs ();
@@ -3667,10 +3665,10 @@ ira (FILE *f)
regstat_compute_ri ();
}
- allocate_initial_values (reg_equivs);
-
overall_cost_before = ira_overall_cost;
- if (ira_conflicts_p)
+ if (! ira_conflicts_p)
+ grow_reg_equivs ();
+ else
{
fix_reg_equiv_init ();
@@ -3686,6 +3684,7 @@ ira (FILE *f)
memset (ira_spilled_reg_stack_slots, 0,
max_regno * sizeof (struct ira_spilled_reg_stack_slot));
}
+ allocate_initial_values (reg_equivs);
timevar_pop (TV_IRA);
Index: ira-emit.c
===================================================================
--- ira-emit.c (revision 171852)
+++ ira-emit.c (working copy)
@@ -900,8 +900,8 @@ modify_move_list (move_t list)
static rtx
emit_move_list (move_t list, int freq)
{
- int cost;
- rtx result, insn;
+ int cost, regno;
+ rtx result, insn, set, to;
enum machine_mode mode;
enum reg_class aclass;
@@ -913,12 +913,34 @@ emit_move_list (move_t list, int freq)
allocno_emit_reg (list->from));
list->insn = get_insns ();
end_sequence ();
- /* The reload needs to have set up insn codes. If the reload
- sets up insn codes by itself, it may fail because insns will
- have hard registers instead of pseudos and there may be no
- machine insn with given hard registers. */
for (insn = list->insn; insn != NULL_RTX; insn = NEXT_INSN (insn))
- recog_memoized (insn);
+ {
+ /* The reload needs to have set up insn codes. If the
+ reload sets up insn codes by itself, it may fail because
+ insns will have hard registers instead of pseudos and
+ there may be no machine insn with given hard
+ registers. */
+ recog_memoized (insn);
+ /* Add insn to equiv init insn list if it is necessary.
+ Otherwise reload will not remove this insn if it decides
+ to use the equivalence. */
+ if ((set = single_set (insn)) != NULL_RTX)
+ {
+ to = SET_DEST (set);
+ if (GET_CODE (to) == SUBREG)
+ to = SUBREG_REG (to);
+ ira_assert (REG_P (to));
+ regno = REGNO (to);
+ if (regno >= ira_reg_equiv_len
+ || (! ira_reg_equiv_invariant_p[regno]
+ && ira_reg_equiv_const[regno] == NULL_RTX))
+ continue; /* regno has no equivalence. */
+ ira_assert (VEC_length (reg_equivs_t, reg_equivs)
+ >= ira_reg_equiv_len);
+ reg_equiv_init (regno)
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
+ }
+ }
emit_insn (list->insn);
mode = ALLOCNO_MODE (list->to);
aclass = ALLOCNO_CLASS (list->to);
