This patch fixes the various bugs that showed up with subversion id 171341 on
the powerpc relating to vector support.
I did a bootstrap and make check. The following tests now pass on a power7
linux/gnu system with these patches, and there were no regressions. Is it ok
to install the patch?
gcc.dg/vect/slp-13.c
gcc.dg/vect/slp-21.c
gcc.dg/vect/slp-reduc-3.c
gcc.dg/vect/vect-10.c
gcc.dg/vect/vect-complex-5.c
gcc.dg/vect/vect-cselim-1.c
gcc.dg/vect/vect-double-reduc-5.c
gcc.dg/vect/vect-outer-1.c
gcc.dg/vect/vect-outer-1a.c
gcc.dg/vect/vect-outer-1b.c
gcc.dg/vect/vect-outer-4f.c
gcc.dg/vect/vect-outer-4g.c
gcc.dg/vect/vect-outer-4k.c
gcc.dg/vect/vect-outer-4l.c
gcc.dg/vect/vect-strided-a-mult.c
gcc.dg/vect/vect-strided-a-u16-i2.c
gcc.dg/vect/vect-strided-a-u16-i4.c
gcc.dg/vect/vect-strided-a-u16-mult.c
gcc.dg/vect/vect-strided-a-u8-i2-gap.c
gcc.dg/vect/vect-strided-a-u8-i8-gap2.c
gcc.dg/vect/vect-strided-a-u8-i8-gap7.c
gcc.dg/vect/vect-strided-mult-char-ls.c
gcc.dg/vect/vect-strided-mult.c
gcc.dg/vect/vect-strided-same-dr.c
gcc.dg/vect/vect-strided-u16-i2.c
gcc.dg/vect/vect-strided-u16-i4.c
gcc.dg/vect/vect-strided-u8-i2-gap.c
gcc.dg/vect/vect-strided-u8-i2.c
gcc.dg/vect/vect-strided-u8-i8-gap2.c
gcc.dg/vect/vect-strided-u8-i8-gap4.c
gcc.dg/vect/vect-strided-u8-i8-gap7.c
gcc.dg/vect/vect-strided-u8-i8.c
gcc.dg/vect/vect-vfa-03.c
2011-03-31 Andrew Pinski <pins...@gmail.com>
Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/48262
* config/rs6000/vector.md (movmisalign<mode>): Allow for memory
operands, as per the specifications.
* config/rs6000/altivec.md (vec_extract_evenv4si): Correct modes.
(vec_extract_evenv4sf): Ditto.
(vec_extract_evenv8hi): Ditto.
(vec_extract_evenv16qi): Ditto.
(vec_extract_oddv4si): Ditto.
--
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md (revision 171787)
+++ gcc/config/rs6000/vector.md (working copy)
@@ -871,8 +871,8 @@ (define_expand "vec_realign_load_<mode>"
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
;; since the load already handles it.
(define_expand "movmisalign<mode>"
- [(set (match_operand:VEC_N 0 "vfloat_operand" "")
- (match_operand:VEC_N 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
+ (match_operand:VEC_N 1 "any_operand" ""))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md (revision 171787)
+++ gcc/config/rs6000/altivec.md (working copy)
@@ -2422,7 +2422,7 @@ (define_insn "altivec_stvrxl"
(define_expand "vec_extract_evenv4si"
[(set (match_operand:V4SI 0 "register_operand" "")
- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "register_operand" "")]
UNSPEC_EXTEVEN_V4SI))]
"TARGET_ALTIVEC"
@@ -2455,7 +2455,7 @@ (define_expand "vec_extract_evenv4si"
(define_expand "vec_extract_evenv4sf"
[(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
(match_operand:V4SF 2 "register_operand" "")]
UNSPEC_EXTEVEN_V4SF))]
"TARGET_ALTIVEC"
@@ -2487,7 +2487,7 @@ (define_expand "vec_extract_evenv4sf"
}")
(define_expand "vec_extract_evenv8hi"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand" "")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "register_operand" "")]
UNSPEC_EXTEVEN_V8HI))]
@@ -2520,9 +2520,9 @@ (define_expand "vec_extract_evenv8hi"
}")
(define_expand "vec_extract_evenv16qi"
- [(set (match_operand:V4SI 0 "register_operand" "")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand" "")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
+ (match_operand:V16QI 2 "register_operand" "")]
UNSPEC_EXTEVEN_V16QI))]
"TARGET_ALTIVEC"
"
@@ -2554,7 +2554,7 @@ (define_expand "vec_extract_evenv16qi"
(define_expand "vec_extract_oddv4si"
[(set (match_operand:V4SI 0 "register_operand" "")
- (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "register_operand" "")]
UNSPEC_EXTODD_V4SI))]
"TARGET_ALTIVEC"
@@ -2587,7 +2587,7 @@ (define_expand "vec_extract_oddv4si"
(define_expand "vec_extract_oddv4sf"
[(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
(match_operand:V4SF 2 "register_operand" "")]
UNSPEC_EXTODD_V4SF))]
"TARGET_ALTIVEC"
