https://gcc.gnu.org/g:ebe3818ac8e4390a94ee99c6501eeb14aa8b4b01
commit r17-2526-gebe3818ac8e4390a94ee99c6501eeb14aa8b4b01 Author: Jiawei <[email protected]> Date: Wed Jun 24 21:45:46 2026 +0800 RISC-V: Add minimal Ssctr extension support This adds minimal support for the Ssctr[1] (Supervisor-mode control transfer records) extension, which depends on Zicsr. gcc/ChangeLog: * config/riscv/riscv-ext.def (ssctr): Add new extension. * config/riscv/riscv-ext.opt: Ditto. * doc/riscv-ext.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/ssctr-version.c: New test. Diff: --- gcc/config/riscv/riscv-ext.def | 13 +++++++++++++ gcc/config/riscv/riscv-ext.opt | 2 ++ gcc/doc/riscv-ext.texi | 4 ++++ gcc/testsuite/gcc.target/riscv/ssctr-version.c | 15 +++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index 449f98a29c5e..2ed1e788d0cf 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1949,6 +1949,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ ssctr, + /* UPPERCASE_NAME */ SSCTR, + /* FULL_NAME */ "Supervisor-mode control transfer records extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ sscsrind, /* UPPERCASE_NAME */ SSCSRIND, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index c25a65a1d60d..d7d0e48d294c 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -389,6 +389,8 @@ Mask(SSCOFPMF) Var(riscv_ss_subext) Mask(SSCOUNTERENW) Var(riscv_ss_subext) +Mask(SSCTR) Var(riscv_ss_subext) + Mask(SSCSRIND) Var(riscv_ss_subext) Mask(SSNPM) Var(riscv_ss_subext) diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index 14d8b928daa5..bebf1c52616a 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -578,6 +578,10 @@ @tab 1.0 @tab Support writeable enables for any supported counter +@item @samp{ssctr} +@tab 1.0 +@tab Supervisor-mode control transfer records extension + @item @samp{sscsrind} @tab 1.0 @tab Supervisor-mode indirect CSR access diff --git a/gcc/testsuite/gcc.target/riscv/ssctr-version.c b/gcc/testsuite/gcc.target/riscv/ssctr-version.c new file mode 100644 index 000000000000..4d119360df50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/ssctr-version.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_ssctr1p0 -mabi=lp64" { target { rv64 } } } */ +/* { dg-options "-mriscv-attribute -march=rv32i_ssctr1p0 -mabi=ilp32" { target { rv32 } } } */ + +#ifndef __riscv_ssctr +#error "Feature macro for 'ssctr' not defined" +#endif + +int +foo (void) +{ + return 0; +} + +/* { dg-final { scan-assembler ".attribute arch, .*ssctr1p0" } } */
