https://gcc.gnu.org/g:c33b7b995f9c932182cc54032b4a747b54070fc6
commit r17-2508-gc33b7b995f9c932182cc54032b4a747b54070fc6 Author: Pan Li <[email protected]> Date: Thu Jul 16 12:57:53 2026 +0800 RISC-V: Add test cases for vfwcvtu.xu.f.v reg overlap Add test cases for vfwcvt.xu.f.v register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-mf2.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vfwcvt_xu-f16-m1.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f16-m2.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f16-m4.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f16-mf2.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f16-mf4.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f32-m1.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f32-m2.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f32-m4.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_xu-f32-mf2.c | 31 ++++++++++++++++++++++ 9 files changed, 195 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m1.c new file mode 100644 index 000000000000..7a8267d8e433 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16m1_t, + vuint32m2_t, + __riscv_vle16_v_f16m1, + __riscv_vfwcvt_xu_f_v_u32m2, + __riscv_vse32_v_u32m2, + vfwcvt_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m2.c new file mode 100644 index 000000000000..668ee6794670 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m2, + vfloat16m2_t, + vuint32m4_t, + __riscv_vle16_v_f16m2, + __riscv_vfwcvt_xu_f_v_u32m4, + __riscv_vse32_v_u32m4, + vfwcvt_xu, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m4.c new file mode 100644 index 000000000000..8e8c3998eca9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m4, + vfloat16m4_t, + vuint32m8_t, + __riscv_vle16_v_f16m4, + __riscv_vfwcvt_xu_f_v_u32m8, + __riscv_vse32_v_u32m8, + vfwcvt_xu, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf2.c new file mode 100644 index 000000000000..e759801700d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16mf2_t, + vuint32m1_t, + __riscv_vle16_v_f16mf2, + __riscv_vfwcvt_xu_f_v_u32m1, + __riscv_vse32_v_u32m1, + vfwcvt_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf4.c new file mode 100644 index 000000000000..184c8ee578e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f16-mf4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16mf4_t, + vuint32mf2_t, + __riscv_vle16_v_f16mf4, + __riscv_vfwcvt_xu_f_v_u32mf2, + __riscv_vse32_v_u32mf2, + vfwcvt_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m1.c new file mode 100644 index 000000000000..45617216db7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m1, + vfloat32m1_t, + vuint64m2_t, + __riscv_vle32_v_f32m1, + __riscv_vfwcvt_xu_f_v_u64m2, + __riscv_vse64_v_u64m2, + vfwcvt_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m2.c new file mode 100644 index 000000000000..8c4b32b83f3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m2, + vfloat32m2_t, + vuint64m4_t, + __riscv_vle32_v_f32m2, + __riscv_vfwcvt_xu_f_v_u64m4, + __riscv_vse64_v_u64m4, + vfwcvt_xu, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m4.c new file mode 100644 index 000000000000..dd8ce67e3805 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m4, + vfloat32m4_t, + vuint64m8_t, + __riscv_vle32_v_f32m4, + __riscv_vfwcvt_xu_f_v_u64m8, + __riscv_vse64_v_u64m8, + vfwcvt_xu, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-mf2.c new file mode 100644 index 000000000000..cfa022d05c88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_xu-f32-mf2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m1, + vfloat32mf2_t, + vuint64m1_t, + __riscv_vle32_v_f32mf2, + __riscv_vfwcvt_xu_f_v_u64m1, + __riscv_vse64_v_u64m1, + vfwcvt_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.xu\.f\.v\s+v30,v31} } } */
