https://gcc.gnu.org/g:13ece0294f16019878b9b2207282a3e52476bcbb
commit r17-642-g13ece0294f16019878b9b2207282a3e52476bcbb Author: Christoph Müllner <[email protected]> Date: Sun May 17 22:49:43 2026 +0200 RISC-V: Add C API and hwprobe feature bit for zicfiss riscv-c-api-doc PR #187 defines the RISC-V C API feature bit for zicfiss as group 1, bit 27. GCC already supports zicfiss, so add the missing feature-bit metadata and libgcc copy of the definition. Upstream Linux exposes zicfiss through RISCV_HWPROBE_KEY_IMA_EXT_1. Copy the upstream Linux hwprobe constants and map the zicfiss bit directly to the matching feature bit. This patch only adds metadata and runtime feature-bit probing. It does not add ISA extension support. gcc/ChangeLog: * common/config/riscv/riscv-ext-bitmask.def: Add zicfiss. * config/riscv/riscv-ext.def: Add C API bit position for zicfiss. libgcc/ChangeLog: * config/riscv/feature_bits.c (ZICFISS_GROUPID, ZICFISS_BITMASK, RISCV_HWPROBE_KEY_IMA_EXT_1, RISCV_HWPROBE_EXT_ZICFISS): Define. (SET_FROM_IMA_EXT_1): Define. (__init_riscv_features_bits_linux): Query IMA_EXT_1 and set zicfiss from the corresponding upstream Linux hwprobe bit. Signed-off-by: Christoph Müllner <[email protected]> Diff: --- gcc/common/config/riscv/riscv-ext-bitmask.def | 1 + gcc/config/riscv/riscv-ext.def | 4 ++-- libgcc/config/riscv/feature_bits.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def index 315ae8fde08a..be12e4bea72d 100644 --- a/gcc/common/config/riscv/riscv-ext-bitmask.def +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def @@ -98,6 +98,7 @@ RISCV_EXT_BITMASK ("zicbop", 1, 25) RISCV_EXT_BITMASK ("zilsd", 1, 8) RISCV_EXT_BITMASK ("zclsd", 1, 9) RISCV_EXT_BITMASK ("zicfilp", 1, 26) +RISCV_EXT_BITMASK ("zicfiss", 1, 27) RISCV_EXT_BITMASK ("zcmp", 1, 10) RISCV_EXT_BITMASK ("zifencei", 1, 11) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index bfa27e725153..71d34470848b 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -346,8 +346,8 @@ DEFINE_RISCV_EXT( /* DEP_EXTS */ ({"zicsr", "zimop"}), /* SUPPORTED_VERSIONS */ ({{1, 0}}), /* FLAG_GROUP */ zi, - /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, - /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 27, /* EXTRA_EXTENSION_FLAGS */ 0) DEFINE_RISCV_EXT( diff --git a/libgcc/config/riscv/feature_bits.c b/libgcc/config/riscv/feature_bits.c index 367473050b42..8d226502eb7a 100644 --- a/libgcc/config/riscv/feature_bits.c +++ b/libgcc/config/riscv/feature_bits.c @@ -184,6 +184,8 @@ struct { #define ZICBOP_BITMASK (1ULL << 25) #define ZICFILP_GROUPID 1 #define ZICFILP_BITMASK (1ULL << 26) +#define ZICFISS_GROUPID 1 +#define ZICFISS_BITMASK (1ULL << 27) #define SET_EXT(EXT) features[EXT##_GROUPID] |= EXT##_BITMASK @@ -268,6 +270,8 @@ struct { #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 +#define RISCV_HWPROBE_KEY_IMA_EXT_1 16 +#define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) struct riscv_hwprobe { long long key; @@ -297,6 +301,9 @@ static long syscall_5_args (long number, long arg1, long arg2, long arg3, #define SET_FROM_IMA_EXT(EXT) \ SET_FROM_HWPROBE (hwprobe_ima_ext, EXT) +#define SET_FROM_IMA_EXT_1(EXT) \ + SET_FROM_HWPROBE (hwprobe_ima_ext_1, EXT) + static void __init_riscv_features_bits_linux () { struct riscv_hwprobe hwprobes[] = { @@ -305,6 +312,7 @@ static void __init_riscv_features_bits_linux () {RISCV_HWPROBE_KEY_MIMPID, 0}, {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0}, {RISCV_HWPROBE_KEY_IMA_EXT_0, 0}, + {RISCV_HWPROBE_KEY_IMA_EXT_1, 0}, }; long res = syscall_5_args (__NR_riscv_hwprobe, (long)&hwprobes, @@ -443,6 +451,9 @@ static void __init_riscv_features_bits_linux () SET_FROM_IMA_EXT (ZCLSD); SET_FROM_IMA_EXT (ZICFILP); + const struct riscv_hwprobe hwprobe_ima_ext_1 = hwprobes[5]; + SET_FROM_IMA_EXT_1 (ZICFISS); + for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; ++i) __riscv_feature_bits.features[i] = features[i];
