https://gcc.gnu.org/g:c360a079623ee703bae51d4be9cf7633b742a57f
commit c360a079623ee703bae51d4be9cf7633b742a57f Author: Alexandre Oliva <[email protected]> Date: Tue Mar 10 04:18:54 2026 -0300 testsuite: vect: ppc: adjust costmodel-pr82255 When vsx is not available and only altivec is enabled, the compiler struggles harder to achieve the desired optimization. Instead of using realigned loads for both arrays vectors in the vect pass, we only use a realigned load for w, but for some reason related with the unknown increment of x in the outer loop, we issue multiple byte loads from x and construct a vector out of it. slp1 comes to the rescue and turns the sequence of loads into a realigned vector load as well. I think we should be able to figure this out in vect, so I'm making this an XFAIL, but with additional checks that we don't lose the desired vectorized load. for gcc/testsuite/ChangeLog * gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c: Adjust expectations for -maltivec -mno-vsx compilations. Diff: --- gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c index 9317ee2e15be..1bd175d7445f 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-pr82255.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-fdump-tree-slp-details" { target { powerpc*-*-* && { ! powerpc_vsx } } } } */ /* PR82255: Ensure we don't require a vec_construct cost when we aren't going to generate a strided load. */ @@ -28,4 +29,14 @@ bar (unsigned char *w, unsigned char *x, int i, int *result) *result = foo (w, 16, x, i); } -/* { dg-final { scan-tree-dump-times "vec_construct" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vec_construct" 0 "vect" { xfail { powerpc*-*-* && { ! powerpc_vsx } } } } } */ +/* Since r15-5523..5559 (we ICEing in between), we've failed the above when + compiling for altivec (selected by check_vect_support_and_set_flags when the + cpu under test doesn't supprot vsx), which makes for a long sequence of byte + loads, but slp comes to the rescue and rearranges the sequence into a single + REALIGN_LOAD, so we get reasonable code in the end. Check that we still do: + vect gets a single REALIGN_LOAD stmt for W, but we also match its add new + stmt note and its value numbering dump. slp1 adds a second REALIGN_LOAD, + this one for X, but we also match its add new stmt note. */ +/* { dg-final { scan-tree-dump-times "REALIGN_LOAD" 3 "vect" { target { powerpc*-*-* && { ! powerpc_vsx } } } } } */ +/* { dg-final { scan-tree-dump-times "REALIGN_LOAD" 3 "slp1" { target { powerpc*-*-* && { ! powerpc_vsx } } } } } */
