https://gcc.gnu.org/g:7ee1dea3d57b80629d44d771b8d7af75efcdfff4
commit 7ee1dea3d57b80629d44d771b8d7af75efcdfff4 Author: Michael Meissner <[email protected]> Date: Thu Mar 5 21:09:08 2026 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 383 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 383 insertions(+) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index b40d1d397589..ee7f1564c684 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,3 +1,386 @@ +==================== Branch work238-dmf, patch #104 ==================== + +Add support for 1,024 bit dense math registers. + +This patch is a prelimianry patch to add the full 1,024 bit dense math register +(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the +DMR register. + +This patch only adds the new 1,024 bit register support. It does not add +support for any instructions that need 1,024 bit registers instead of 512 bit +registers. + +I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit +registers. The 'wD' constraint added in previous patches is used for these +registers. I added support to do load and store of DMRs via the VSX registers, +since there are no load/store dense math instructions. I added the new keyword +'__dm1024' to create 1,024 bit types that can be loaded into dense math +registers. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +This is version 5 of the patches. The previous patches were: + + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html + +gcc/ + +2026-03-05 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. + (UNSPEC_DM_INSERT512_LOWER): Likewise. + (UNSPEC_DM_EXTRACT512): Likewise. + (UNSPEC_DM_RELOAD_FROM_MEMORY): Likewise. + (UNSPEC_DM_RELOAD_TO_MEMORY): Likewise. + (movtdo): New define_expand and define_insn_and_split to implement 1,024 + bit dense math registers. + (movtdo_insert512_upper): New insn. + (movtdo_insert512_lower): Likewise. + (movtdo_extract512): Likewise. + (reload_tdo_from_memory): Likewise. + (reload_tdo_to_memory): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add dense math + register support. + (rs6000_init_builtins): Add support for __dm1024 keyword. + * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support + for TDOmode. + (rs6000_function_arg): Likewise. + * config/rs6000/rs6000-modes.def (TDOmode): New mode. + * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add + support for TDOmode. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_hard_regno_mode_ok): Likewise. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload + hooks for dense math TDO reload mode. + (reg_offset_addressing_ok_p): Add support for TDOmode. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_mangle_type): Add mangling for __dm1024 type. + (rs6000_dense_math_register_move_cost): Add support for TDOmode. + (rs6000_split_multireg_move): Likewise. + (rs6000_invalid_conversion): Likewise. + * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. + (enum rs6000_builtin_type_index): Add dense math register type nodes. + (dm1024_type_node): Likewise. + (ptr_dm1024_type_node): Likewise. + +gcc/testsuite/ + +2026-03-05 Michael Meissner <[email protected]> + + * gcc.target/powerpc/dm-1024bit.c: New test. + +==================== Branch work238-dmf, patch #103 ==================== + +Make the MMA instructions support -mdense-math. + +This patch completes support for the dense math registes with 512-bit types. +The MMA insns have been modfiied to use the 'wD' constraint and the +accumulator_operand predicate. + +The insn (mma_xxsetaccz) that clears accumulators has been changed to be a +normal unspec when -mdense-math. If -mno-dense-math is in effect, the insn +remains an unspec_volatile due to register constraints and the need to issue a +de-prime operation. + +I added a comment in front of each insn to say which instructions are generated +by the insns. + +I set -mcpu=future to turn on -mdense-math. + +I added 2 tests to the testsuite for -mdense-math support. + +A future path will add support for 1,024-bit dense registers. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +This is version 4 of the patches. The previous patches were: + + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707452.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707453.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707454.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707455.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707456.html + +gcc/ + +2026-03-05 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec. + (mma_xxsetaccz) Convert to being a define_expand that can handle both + the original MMA support without dense math registers, and support with + dense math register support. + (mma_xxsetaccz_nodm): Rename original mma_xxsetaccz, and restrict this + to when we do not have dense math registers. + (mma_xxsetaccz_dm): New insn for clearing dense math registers. + (mma_<acc>): Add support for dense registers. + Document which instructions are generated by each insn. + (mma_<vv>): Likewise. + (mma_<avv>): Likewise. + (mma_<pv>): Likewise. + (mma_<apv>): Likewise. + (mma_<vvi4i4i8>): Likewise. + (mma_<avvi4i4i8>): Likewise. + (mma_<vvi4i4i2>): Likewise. + (mma_<avvi4i4i2): Likewise. + (mma_<vvi4i4>): Likewise. + (mma_<avvi4i4>): Likewise. + (mma_<pvi4i2>): Likewise. + (mma_<apvi4i2>): Likewise. + (mma_<vvi4i4i4>): Likewise. + (mma_<avvi4i4i4>): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do + not issue a xxmfacc instruction if we support dense math registers. + * config/rs6000/rs6000-cpu.def (FUTURE_MASKS_SERVER): If -mcpu=future, + turn on -mdense-math. + (POWERPC_MASKS): Mark -mdense-math as being set by -mcpu=<xxx> options. + +gcc/testsuite/ + +2026-03-05 Michael Meissner <[email protected]> + + * gcc.target/powerpc/mma-dm-1.c: New test. + * gcc.target/powerpc/mma-dm-1.c: Likewise. + * lib/target-supports.exp + (check_effective_target_powerpc_dense_math_ok): New powerpc target + support. + +==================== Branch work238-dmf, patch #102 ==================== + +Add support for dense math registers. + +This patch adds basic support for dense math registers. It includes support for +moving values to/from dense registers. The MMA instructions are not yet +modified to know about dense math registers. The -mcpu=future option does not +set -mdense-math in this patch. A future patch will make these changes. + +The changes from the V3 patches include: + + 1: XOmode moves include moving to/from dense math registers. + + 2: Add predicate dense_math_operand. + + 3: Make the predicate accumulator_operand match on dense math registers. + + 4: Add dense math register class. + + 5: Add the 8 dense math register accumulators with internal register + numbers 111-118. + + 6: Make the 'wD' constraint match dense math register if -mdense-math, and + 4 adjacent VSX register if -mno-dense-math is in effect. + + 7: Set up the reload information so that the register allocator knows that + dense math registers do not have load or store instructions. Instead to + read/write dense math registers, you have to use VSX registers as + intermediaries. + + 8: Make the print_operand '%A' output operand now knows about accumulators + in dense math registrs and accumulators in 4 adjacent VSX registers. + + 9: Update register move and memmory load/store costs for dense math + registers. + + 10: Make dense math registers a pressure class for register allocation. + + 11: Do not issue MMA deprime instructions if -mdense-math is in effect. + + 12: Add support for dense math registers to rs6000_split_multireg_move. + +The changes from V4 patches include: + + 1: Use the new TARGET_MMA_DENSE_MATH and TARGET_MMA_NO_DENSE_MATH macros + in the compiler. + + 2: Allow XOmode mode to be used if the user did -mno-mma -mcpu=future. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +This is version 5 of the patches. The previous patches were: + + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html + +gcc/ + +2026-03-05 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (movxo): Convert to being a define_expand that + can handle both the original MMA support without dense math registes, + and adding dense math support. + (movxo_nodm): Rename original movxo insn, and restrict this insn to when + we do not have dense math registers. + (movxo_dm): New define_insn_and_split for dense math registers. + * config/rs6000/predicates.md (dense_math_operand): New predicate. + (accumulator_operand): Add support for dense math registes. + * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add dense math + register support. + (enum rs6000_reload_reg_typ): Likewise. + (LAST_RELOAD_REG_CLASS): Likewise. + (reload_reg_map): Likewise. + (rs6000_reg_names): Likewise. + (alt_reg_names): Likewise. + (rs6000_hard_regno_nregs_internal): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_secondary_reload_memory): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_secondary_reload_class): Likewise. + (print_operand): Likewise. + (rs6000_dense_math_register_move_cost): New helper function. + (rs6000_register_move_cost): Add dense math register support. + (rs6000_memory_move_cost): Likewise. + (rs6000_compute_pressure_classes): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Likewise. + (rs6000_split_multireg_move): Likewise. + * config/rs6000/rs6000.h (UNITS_PER_DM_WORD): New macro. + (FIRST_PSEUDO_REGISTER): Add dense math register support. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (DM_REGNO_P): New macro. + (enum reg_class): Add dense math register support. + (REG_CLASS_NAMES): Likewise. + (REGISTER_NAMES): Likewise. + (ADDITIONAL_REGISTER_NAMES): Likewise. + * config/rs6000/rs6000.md (FIRST_DM_REGNO): New constant. + (LAST_DM_REGNO): Likewise. + + +==================== Branch work238-dmf, patch #101 ==================== + +Add the -mdense-math option. + +This patch adds the -mdense-math option for -mcpu=future. The next set of +patches will support for using dense math registers with the MMA instructions. +All this patch does is add the option. A future patch will implement support +for dense math registers, and another patch will then switch the MMA +instructions to use dense math registers. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +This is version 5 of the patches. The previous patches were: + + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html + +Between V4 and V5, this patch adds macros to say whether MMA supports ISA 3.1 +accumulators being overlaid over VSX registers 0..31 or whether it supports +dense math accumulators. + +For users, the following macros are defined: + + __MMA_NO_DENSE_MATH__ ISA 3.1 MMA support. + __MMA_DENSE_MATH__ MMA with dense math registers. + +Within the compiler, the following macros are defined: + + TARGET_MMA_NO_DENSE_MATH ISA 3.1 MMA support. + TARGET_MMA_DENSE_MATH MMA with dense math registers. + +gcc/ + +2026-03-05 Michael Meissner <[email protected]> + + * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define + __MMA_DENSE_MATH__ if we have MMA that uses dense math register + accumulators. Define __MMA_NO_DENSE_MATH__ if we have MMA but we are + using ISA 3.1 where the accumulators are overlaid over VSX registers + 0..32. Define __DENSE_MATH__ if we have dense math registers. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not + allow -mdense-math unless -mcpu=future is used. + (rs6000_opt_masks): Add -mdense-math support. + * config/rs6000/rs6000.h (TARGET_MMA_DENSE_MATH): New macro. + (TARGET_MMA_NO_DENSE_MATH): Likewise. + * config/rs6000/rs6000.opt (-mdense-math): New option. + * doc/invoke.texi (RS/6000 and PowerPC Options): Add -mdense-math. + +==================== Branch work238-dmf, patch #100 ==================== + +Add wD constraint. + +This patch adds a new constraint ('wD') that matches the accumulator registers +used by the MMA instructions. Possible future PowerPC machines are thinking +about having a new set of 8 dense math accumulators that will be 1,024 bits in +size. The 'wD' constaint was chosen because the VSX constraints start with 'w'. +The 'wd' constraint was already used, so I chose 'wD' to be similar. + +To change code to possibly use dense math registers, the 'd' constraint should +be changed to 'wD', and the predicate 'fpr_reg_operand' should be changed to +'accumulator_operand'. + +On current power10/power11 systems, the accumulators overlap with the 32 +traditional FPR registers (i.e. VSX vector registers 0..31). Each accumulator +uses 4 adjacent FPR/VSX registers for a 512 bit logical register. + +Possible future PowerPC machines would have these 8 accumulator registers be +separate registers, called dense math registers. It is anticipated that when in +dense math register mode, the MMA instructions would use the accumulators +instead of the adjacent VSX registers. I.e. in power10/power11 mode, +accumulator 1 will overlap with vector registers 4-7, but in dense math register +mode, accumulator 1 will be a separate register. + +Code compiled for power10/power11 systems will continue to work on the potential +future machine with dense math register support but the compiler will have fewer +vector registers available for allocation because it believe the accumulators +are using vector registers. For example, the file mma-double-test.c in the +gcc.target/powerpc testsuite directory has 8 more register spills to/from the +stack for power10/power11 code then when compiled with dense math register +support. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +This is version 5 of the patches. The previous patches were: + + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html + * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html + +In this patch, I have removed using the wD constriant in mma.md. A later patch +will change mma.md to using wA instead of a d constraint. + +2026-03-05 Michael Meissner <[email protected]> + + * config/rs6000/constraints.md (wD): New constraint. + * config/rs6000/predicates.md (accumulator_operand): New predicate. + * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Print the register + class for the 'wD' constraint. + (rs6000_init_hard_regno_mode_ok): Set up the 'wD' register constraint + class. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add element for + the 'wD' constraint. + * doc/md.texi (PowerPC constraints): Document the 'wD' constraint. + ==================== Branch work238-dmf, baseline ==================== 2026-03-05 Michael Meissner <[email protected]>
