https://gcc.gnu.org/g:36faa08b72c8159b143a970540a753c6a00159de
commit 36faa08b72c8159b143a970540a753c6a00159de Author: Michael Meissner <[email protected]> Date: Tue Mar 3 17:28:53 2026 -0500 Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers used by the MMA instructions. Possible future PowerPC machines are thinking about having a new set of 8 dense math accumulators that will be 1,024 bits in size. The 'wD' constaint was chosen because the VSX constraints start with 'w'. The 'wd' constraint was already used, so I chose 'wD' to be similar. To change code to possibly use dense math registers, the 'd' constraint should be changed to 'wD', and the predicate 'fpr_reg_operand' should be changed to 'accumulator_operand'. On current power10/power11 systems, the accumulators overlap with the 32 traditional FPR registers (i.e. VSX vector registers 0..31). Each accumulator uses 4 adjacent FPR/VSX registers for a 512 bit logical register. Possible future PowerPC machines would have these 8 accumulator registers be separate registers, called dense math registers. It is anticipated that when in dense math register mode, the MMA instructions would use the accumulators instead of the adjacent VSX registers. I.e. in power10/power11 mode, accumulator 1 will overlap with vector registers 4-7, but in dense math register mode, accumulator 1 will be a separate register. Code compiled for power10/power11 systems will continue to work on the potential future machine with dense math register support but the compiler will have fewer vector registers available for allocation because it believe the accumulators are using vector registers. For example, the file mma-double-test.c in the gcc.target/powerpc testsuite directory has 8 more register spills to/from the stack for power10/power11 code then when compiled with dense math register support. The patches have been tested on both little and big endian systems. Can I check it into the master branch? This is version 4 of the patches. The previous patches were: * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707452.html * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707453.html * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707454.html * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707455.html * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/707456.html In this patch, I have removed using the wD constriant in mma.md. A later patch will change mma.md to using wA instead of a d constraint. 2026-03-03 Michael Meissner <[email protected]> * config/rs6000/constraints.md (wD): New constraint. * config/rs6000/predicates.md (accumulator_operand): New predicate. * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Print the register class for the 'wD' constraint. (rs6000_init_hard_regno_mode_ok): Set up the 'wD' register constraint class. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add element for the 'wD' constraint. * doc/md.texi (PowerPC constraints): Document the 'wD' constraint. Diff: --- gcc/config/rs6000/rs6000-c.cc | 4 ++++ gcc/config/rs6000/rs6000.cc | 10 ++++++++++ gcc/config/rs6000/rs6000.opt | 4 ++++ gcc/doc/invoke.texi | 7 +++++++ 4 files changed, 25 insertions(+) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index eb6a881aa9bd..a7eb951b014d 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -590,6 +590,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); + /* Tell the user if we support the dense math registers for use with MMA and + cryptography. */ + if ((flags & OPTION_MASK_DENSE_MATH) != 0) + rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__"); /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3454a090dbc2..68d5e95179f7 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4410,6 +4410,15 @@ rs6000_option_override_internal (bool global_init_p) if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; + /* Turn off dense math register support on non-future systems. */ + if (TARGET_DENSE_MATH && !TARGET_FUTURE) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0) + error ("%qs requires %qs", "-mdense-math", "-mcpu=future"); + + rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH; + } + if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags); @@ -24463,6 +24472,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = false, true }, { "cmpb", OPTION_MASK_CMPB, false, true }, { "crypto", OPTION_MASK_CRYPTO, false, true }, + { "dense-math", OPTION_MASK_DENSE_MATH, false, true }, { "direct-move", 0, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 9f3519da77b2..f836d1982877 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -639,6 +639,10 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +mdense-math +Target Mask(DENSE_MATH) Var(rs6000_isa_flags) +Generate (do not generate) instructions that use dense math registers. + ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 56bd4b35e9ae..eb774b0c622f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -32675,6 +32675,13 @@ This option is enabled by default. Enable or disable warnings about deprecated @samp{vector long ...} Altivec type usage. This option is enabled by default. +@opindex mdense-math +@opindex mno-dense-math +@item -mdense-math +@itemx -mno-dense-math +Generate (do not generate) code that uses the dense math registers. +This option is enabled by default. + @end table @node RX Options
