https://gcc.gnu.org/g:a7d442ab3180fe68382f24436a7f369ae77d7898
commit r16-7148-ga7d442ab3180fe68382f24436a7f369ae77d7898 Author: Robin Dapp <[email protected]> Date: Wed Jan 28 17:54:42 2026 +0100 RISC-V: testsuite: Add zvl requirement to PR123626. This adds a new require-effective-target check to pr123626.c. As the test is a run test compiled with _zvl256b we need to ensure the target actually supports 256b vectors. We can only check for exactly 256b right now (rvv_zvl256b_ok), i.e. "VLS". Therefore, the patch also adds a new target check rvv_zvl_ge_256b_ok where ge means greater or equal. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add rvv_zvl_ge_256b_ok. * gcc.target/riscv/rvv/base/pr123626.c: Use new target check. Diff: --- gcc/testsuite/gcc.target/riscv/rvv/base/pr123626.c | 2 ++ gcc/testsuite/lib/target-supports.exp | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr123626.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr123626.c index ddf9b065d91e..b7ef113cbcc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr123626.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr123626.c @@ -1,6 +1,8 @@ /* { dg-do run } */ /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fsigned-char -fno-strict-aliasing -fwrapv -std=gnu99" { target rv64 } } */ /* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32 -O3 -fsigned-char -fno-strict-aliasing -fwrapv -std=gnu99" { target rv32 } } */ +/* { dg-require-effective-target rvv_zvl_ge_256b_ok } */ + short a; long long b; char c[3][3][17]; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 87c216644224..72a8eebbcb11 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2163,6 +2163,24 @@ proc check_effective_target_rvv_zvl256b_ok { } { } "-march=${gcc_march}"] } +# Return 1 if the target runtime supports at least 256-bit +# vectors, 0 otherwise. Cache the result. + +proc check_effective_target_rvv_zvl_ge_256b_ok { } { + # Check if the target has at least a VLENB of 32. + set gcc_march [riscv_get_arch] + return [check_runtime ${gcc_march}_exec { + int main() + { + int vlenb = 0; + asm ("csrr %0,vlenb" : "=r" (vlenb) : : ); + if (vlenb >= 32) + return 0; + return 1; + } + } "-march=${gcc_march}"] +} + # Return 1 if the target runtime supports 512-bit vectors, 0 otherwise. # Cache the result.
