https://gcc.gnu.org/g:bcfc957f0b8815d1a323a8948140c219edd274bc
commit bcfc957f0b8815d1a323a8948140c219edd274bc Author: Michael Meissner <[email protected]> Date: Fri Dec 12 02:48:39 2025 -0500 Add -mbfloat16-combine for testing. 2025-12-12 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (extendbf<mode>): Disable if -mbfloat16-combine. * config/rs6000/rs6000.opt (-mbfloat16-combine): New debug option. Diff: --- gcc/config/rs6000/float16.md | 2 +- gcc/config/rs6000/rs6000.opt | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 0fb5e20300dd..685aba48805f 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -234,7 +234,7 @@ (float_extend:SFDF (match_operand:BF 1 "vsx_register_operand" "v"))) (clobber (match_scratch:V8BF 2 "=v"))] - "TARGET_BFLOAT16_HW" + "TARGET_BFLOAT16_HW && !TARGET_BFLOAT16_COMBINE" "#" "&& 1" [(pc)] diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index a392a63cdfc0..2faba44ed9ee 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -647,6 +647,10 @@ mbfloat16-vector Target Var(TARGET_BFLOAT16_VECTOR) Init(0) Save Undocumented Change the code for bfloat16 conversions. +mbfloat16-combine +Target Var(TARGET_BFLOAT16_COMBINE) Init(0) Save Undocumented +Change the code for bfloat16 conversions #2. + ; Documented parameters -param=rs6000-vect-unroll-limit=
