https://gcc.gnu.org/g:2d26dcdbcb43ca5b8a3d2e61c7defc3d8a3d55ce
commit r16-5560-g2d26dcdbcb43ca5b8a3d2e61c7defc3d8a3d55ce Author: John David Anglin <[email protected]> Date: Mon Nov 24 14:38:49 2025 -0500 hppa: Update peephole2 patterns for scaled/unscaled indexed loads and stores The peephole2 patterns to optimize scaled/unscaled indexed loads and stores are updated to ensure the REG_POINTER flag is set/unset in the base/index regs on targets with non-equivalent space registers. Previously, unscaled indexed loads and stores were only optimized on targets with equivalent space registers. We can now optimize these instructions on targets with non-equivalent space registers. 2025-11-24 John David Anglin <[email protected]> gcc/ChangeLog: * config/pa/pa.h (REGS_OK_FOR_BASE_INDEX): New define. * config/pa/pa.md: Update peephole2 patterns for scaled/unscaled indexed loads and stores. Diff: --- gcc/config/pa/pa.h | 10 +++++++++ gcc/config/pa/pa.md | 65 +++++++++++++++++++---------------------------------- 2 files changed, 33 insertions(+), 42 deletions(-) diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 6972faae8ec4..b8756dfbd146 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -860,6 +860,16 @@ extern int may_call_alloca; || REGNO (X) == FRAME_POINTER_REGNUM \ || REGNO (X) >= FIRST_PSEUDO_REGISTER)) +/* Nonzero if X and Y are hard regs that can be used as base + and index regs in an unscaled index address. This is only + used after reload. */ +#define REGS_OK_FOR_BASE_INDEX(X,Y) \ + (REGNO (X) && REGNO (X) < 32 \ + && REGNO (Y) && REGNO (Y) < 32 \ + && (TARGET_NO_SPACE_REGS \ + || (REG_POINTER (X) && !REG_POINTER (Y)) \ + || (!REG_POINTER (X) && REG_POINTER (Y)))) + /* Nonzero if X is a hard reg that can be used as an index. */ #define STRICT_REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 23129940e644..99ab06e2d3e1 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2346,6 +2346,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) (match_dup 3)) @@ -2364,6 +2365,7 @@ && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2))) (match_dup 3)) @@ -2379,9 +2381,7 @@ (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -2396,9 +2396,7 @@ (match_operand:SI 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -2414,9 +2412,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -2432,9 +2428,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -3961,6 +3955,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) (match_dup 3)) @@ -3978,6 +3973,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2))) (match_dup 3)) @@ -3996,6 +3992,7 @@ && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2))) (match_dup 3)) @@ -4014,6 +4011,7 @@ && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2))) (match_dup 3)) @@ -4029,9 +4027,7 @@ (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -4046,9 +4042,7 @@ (match_operand:DF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -4064,9 +4058,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -4082,9 +4074,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -4355,6 +4345,7 @@ && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2))) (match_dup 3)) @@ -4371,9 +4362,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -4389,9 +4378,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -4625,6 +4612,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2))) (match_dup 3)) @@ -4643,6 +4631,7 @@ && !TARGET_DISABLE_INDEXING && TARGET_64BIT && REG_OK_FOR_BASE_P (operands[2]) + && (TARGET_NO_SPACE_REGS || REG_POINTER (operands[2])) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2))) (match_dup 3)) @@ -4658,9 +4647,7 @@ (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -4675,9 +4662,7 @@ (match_operand:SF 3 "register_operand" ""))] "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1))) (match_dup 3)) @@ -4693,9 +4678,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_INDEX_P (operands[1]) - && REG_OK_FOR_BASE_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2))) (match_dup 3)) @@ -4711,9 +4694,7 @@ "!TARGET_SOFT_FLOAT && !TARGET_DISABLE_INDEXING && TARGET_64BIT - && TARGET_NO_SPACE_REGS - && REG_OK_FOR_BASE_P (operands[1]) - && REG_OK_FOR_INDEX_P (operands[2]) + && REGS_OK_FOR_BASE_INDEX (operands[1], operands[2]) && FP_REGNO_P (REGNO (operands[3]))" [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1))) (match_dup 3))
