https://gcc.gnu.org/g:a787d411166382055d6b4502133ee25db5852927
commit a787d411166382055d6b4502133ee25db5852927
Author: Pan Li <pan2...@intel.com>
Date: Fri Sep 12 19:57:28 2025 +0800
RISC-V: Add test for vec_duplicate + vwaddu.vv signed combine with GR2VR
cost 0, 1 and 15
Add asm dump check and run test for vec_duplicate + vwaddu.vv
combine to vwaddu.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
for vwaddu.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit b653093572c1fb9f489ed7e3add20a6b081b0b9e)
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 4 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 4 ++
.../riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c | 18 +++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h | 34 ++++++++++
.../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 79 ++++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h | 27 ++++++++
13 files changed, 194 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index d191097e2bb3..bb29ef5638cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint16_t
+#define NT uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index e0b4b732c79c..1d738571b498 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint32_t
+#define NT uint16_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 65528400b5b4..dc6d1c6b1837 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint64_t
+#define NT uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -29,3 +32,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 23479d97b650..c6da9c7e19d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint16_t
+#define NT uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 8c41bd85686b..6f1adef686c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint32_t
+#define NT uint16_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index abe16cd7b509..5ea7cc96ae66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint64_t
+#define NT uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index f232d6a97bd7..f18409e76432 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint16_t
+#define NT uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 24e187ce2b05..b33d8269136b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint32_t
+#define NT uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 977aa463232e..40f4142a88a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -3,11 +3,14 @@
#include "vx_binary.h"
#include "vx_ternary.h"
+#include "vx_widen.h"
#define T uint64_t
+#define NT uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
+TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
/* { dg-final { scan-assembler-not {vmadd.vx} } } */
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c
new file mode 100644
index 000000000000..e7a75d56f774
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT uint64_t
+#define NT uint32_t
+#define NAME add
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+ RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_vx_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
new file mode 100644
index 000000000000..646edab4310d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -0,0 +1,34 @@
+#ifndef HAVE_DEFINED_VX_VF_BINARY_WIDEN_H
+#define HAVE_DEFINED_VX_VF_BINARY_WIDEN_H
+
+#include <stdint.h>
+
+#undef HAS_INT128
+
+#if __riscv_xlen == 64
+#define HAS_INT128
+typedef unsigned __int128 uint128_t;
+typedef signed __int128 int128_t;
+#endif
+
+#define DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME) \
+void \
+test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \
+ NT * restrict vs2, \
+ NT rs1, unsigned n) \
+{ \
+ for (unsigned i = 0; i < n; i++) \
+ vd[i] = (WT)vs2[i] OP (WT)rs1; \
+}
+
+#define DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, OP, NAME) \
+ DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME)
+#define RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) \
+ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0(vd, vs2, rs1, n)
+#define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
+ RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n)
+
+#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \
+ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add)
+
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
new file mode 100644
index 000000000000..48dc4d4c8496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -0,0 +1,79 @@
+#ifndef HAVE_DEFINED_VX_WIDEN_DATA_H
+#define HAVE_DEFINED_VX_WIDEN_DATA_H
+
+#define N 16
+
+#define DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) \
+ binary_widen_##WT##_##NT##_##NAME##_s
+#define DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME)
+
+#define DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) \
+ struct DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME)
+#define DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME)
+
+#define DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) \
+ binary_widen_##WT##_##NT##_##NAME##_data
+#define DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME)
+
+#define DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME)
+
+#define DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \
+ { \
+ NT vs2[N]; \
+ NT rs1; \
+ WT expect[N]; \
+ WT vd[N]; \
+ };
+#define DEF_BINARY_WIDEN_STRUCT_0_WRAP(WT, NT, NAME) \
+ DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME)
+
+DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
+
+DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
+ {
+ /* vs2 */
+ {
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ },
+ /* rs1 */
+ 2147483647,
+ /* expect */
+ {
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ },
+ {
+ /* vs2 */
+ {
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ },
+ /* rs1 */
+ 4294967295,
+ /* expect */
+ {
+ 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull,
+ 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+ 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull,
+ 8589934589ull, 8589934589ull, 8589934589ull, 8589934589ull,
+ },
+ },
+};
+
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h
new file mode 100644
index 000000000000..87fe0b132152
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h
@@ -0,0 +1,27 @@
+#ifndef HAVE_DEFINED_VX_WIDEN_RUN_H
+#define HAVE_DEFINED_VX_WIDEN_RUN_H
+
+int
+main ()
+{
+ unsigned i, k;
+
+ for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++)
+ {
+ DATA_TYPE *data = &TEST_DATA[i];
+ NT *vs2 = data->vs2;
+ NT rs1 = data->rs1;
+ WT *expect = data->expect;
+ WT *vd = data->vd;
+
+ TEST_RUN (WT, NT, NAME, vd, vs2, rs1, N);
+
+ for (k = 0; k < N; k++)
+ if (vd[k] != expect[k])
+ __builtin_abort ();
+ }
+
+ return 0;
+}
+
+#endif
