https://gcc.gnu.org/g:1e6db83e8f43481f392203e9e2636e6d27e76624
commit 1e6db83e8f43481f392203e9e2636e6d27e76624
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Sun Sep 21 22:42:52 2025 -0400
Revert changes
Diff:
---
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-string.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 6 +++---
gcc/config/rs6000/rs6000.h | 20 +++++++++-----------
gcc/config/rs6000/rs6000.md | 18 +++++++++---------
6 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 4c6306c3c607..825e7c54e73e 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POWER7"
+ "TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index dfbb7d02157b..bc1580f051b0 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P6_64:
return TARGET_CMPB && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POWER7;
+ return TARGET_POPCNTD;
case ENB_P7_64:
- return TARGET_POWER7 && TARGET_POWERPC64;
+ return TARGET_POPCNTD && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 4ba7ef6bdb42..561297b0ba46 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes,
unsigned int base_align,
bool
expand_block_compare (rtx operands[])
{
- /* TARGET_POWER7 is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POWER7);
+ /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
+ gcc_assert (TARGET_POPCNTD);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 241d18548209..c599d864b3a7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1927,7 +1927,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POWER7 && mode == SImode)
+ if (TARGET_POPCNTD && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3925,7 +3925,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POWER7)
+ else if (TARGET_POPCNTD)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4138,7 +4138,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
{
if (global_options.x_rs6000_ieeequad
- && (!TARGET_POWER7 || !TARGET_VSX))
+ && (!TARGET_POPCNTD || !TARGET_VSX))
error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 643aa2449318..1bd2ce53cc7b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -443,7 +443,7 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
@@ -451,17 +451,17 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POWER7) /* ISA 2.06 */
+ || TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
#define TARGET_LFIWAX TARGET_CMPB
-#define TARGET_LFIWZX TARGET_POWER7
-#define TARGET_FCFIDS TARGET_POWER7
-#define TARGET_FCFIDU TARGET_POWER7
-#define TARGET_FCFIDUS TARGET_POWER7
-#define TARGET_FCTIDUZ TARGET_POWER7
-#define TARGET_FCTIWUZ TARGET_POWER7
+#define TARGET_LFIWZX TARGET_POPCNTD
+#define TARGET_FCFIDS TARGET_POPCNTD
+#define TARGET_FCFIDU TARGET_POPCNTD
+#define TARGET_FCFIDUS TARGET_POPCNTD
+#define TARGET_FCTIDUZ TARGET_POPCNTD
+#define TARGET_FCTIWUZ TARGET_POPCNTD
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
#define TARGET_CTZ TARGET_MODULO
@@ -528,7 +528,7 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POWER7 /* ISA 2.06 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -558,8 +558,6 @@ extern int rs6000_vector_align[];
/* ISA bits that are set via -mcpu=<xxx>, but that do not have an associated
switch with the option. */
-#define TARGET_POWER7 \
- ((rs6000_cpu_option_flags & CPU_OPTION_POWER7_MASK) != 0)
#define TARGET_POWER8 \
((rs6000_cpu_option_flags & CPU_OPTION_POWER8_MASK) != 0)
#define TARGET_POWER9 \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 71585dde89db..a78e1118f50d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -387,7 +387,7 @@
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POWER7"))
+ (match_test "TARGET_POPCNTD"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -6801,7 +6801,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POWER7"
+ "TARGET_HARD_FLOAT && TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6809,7 +6809,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POWER7"
+ "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -10173,7 +10173,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14440,7 +14440,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14818,7 +14818,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14826,7 +14826,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14834,7 +14834,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14849,7 +14849,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
