https://gcc.gnu.org/g:d99645a5f61c7030a85826e5fe2044abd8ac3ca9
commit d99645a5f61c7030a85826e5fe2044abd8ac3ca9
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Sun Sep 21 18:27:14 2025 -0400
Remove internal -mpower9-misc support.
2025-09-21 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/dfp.h (dfptstsfi_<code>_<mode>): Change
TARGET_P9_MISC
to TARGET_POWER9.
(dfp_sgnfcnc_<mode): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Remove
OPTION_MASK_P9_MISC.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-string.cc (do_load_mask_compare): Change
TARGET_P9_MISC to TARGET_POWER9.
(do_overlap_load_compare): Likewise.
(expand_compare_loop): Likewise.
(expand_block_compare_gpr): Likewise.
(expand_block_compare): Likewise.
* config/rs6000/rs6000.md (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Remove -mpower9-misc.
* config/rs6000/rs6000.h (TARGET_POWER9): New macro.
* config/rs6000/rs6000.md (rs6000_mffscrn): Change TARGET_P9_MISC to
TARGET_POWER9.
(rs6000_mffscrni): Likewise.
(rs6000_mffscdrn): Likewise.
(rs6000_set_fpscr_rn): Likewise.
(rs6000_set_fpscr_drn): Likewise.
(rs6000_mffsl): Likewise.
(darn_32_<mode>): Likewise.
(darn_64_<mode>): Likewise.
(darn_raw_<mode>): Likewise.
(@darn<mode>): Likewise.
(cmprb): Likewise.
(cmprb_internal): Likewise.
(setb_signed): Likewise.
(setb_unsigned): Likewise.
(cmprb2): Likewise.
(cmprb2_internal): Likewise.
(cmpeqb): Likewise.
(cmpeqb_internal): Likewise.
* config/rs6000/rs6000.opt (-mpower9-misc): Change to WarnRemoved.
Diff:
---
gcc/config/rs6000/dfp.md | 4 ++--
gcc/config/rs6000/rs6000-cpus.def | 2 --
gcc/config/rs6000/rs6000-string.cc | 26 +++++++++++++-------------
gcc/config/rs6000/rs6000.cc | 3 +--
gcc/config/rs6000/rs6000.h | 2 ++
gcc/config/rs6000/rs6000.md | 36 ++++++++++++++++++------------------
gcc/config/rs6000/rs6000.opt | 3 +--
7 files changed, 37 insertions(+), 39 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 59fa66ae15c8..825e7c54e73e 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -347,7 +347,7 @@
(DFP_TEST:SI (match_dup 3)
(const_int 0)))
]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode))
{
@@ -365,7 +365,7 @@
(match_operand:DDTD 2 "gpc_reg_operand" "d")]
UNSPEC_DTSTSFI)
(match_operand:SI 3 "zero_constant" "j")))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
/* If immediate operand is greater than 63, it will behave as if
the value had been 63. The code generator does not support
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index bec532f42b80..bc2823762837 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -106,7 +106,6 @@
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
- | OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR) \
& ~OTHER_FUSION_MASKS)
@@ -175,7 +174,6 @@
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
- | OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 3d2911ca08a0..561297b0ba46 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -539,7 +539,7 @@ do_load_mask_compare (const machine_mode load_mode, rtx
diff, rtx cmp_rem, rtx d
emit_insn (gen_lshrsi3 (d2, d2, shift_amount));
}
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later. */
rtx cmp = gen_rtx_COMPARE (CCUNSmode, d1, d2);
@@ -605,7 +605,7 @@ do_overlap_load_compare (machine_mode load_mode, bool
isConst,
do_load_for_compare_from_addr (load_mode, d1, addr1, orig_src1);
do_load_for_compare_from_addr (load_mode, d2, addr2, orig_src2);
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later. */
rtx cmp = gen_rtx_COMPARE (CCUNSmode, d1, d2);
@@ -1185,7 +1185,7 @@ expand_compare_loop (rtx operands[])
rtx dcond = NULL_RTX; /* Used for when we jump to diff_label. */
/* For p9 we need to have just one of these as multiple places define
it and it gets used by the setb at the end. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
dcond = gen_reg_rtx (CCUNSmode);
if (!bytes_is_const || bytes >= loop_bytes)
@@ -1227,7 +1227,7 @@ expand_compare_loop (rtx operands[])
src2_ix2, orig_src2);
do_add3 (iv2, iv2, GEN_INT (loop_bytes));
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later. */
rtx cmp = gen_rtx_COMPARE (CCUNSmode, d1_1, d2_1);
@@ -1245,7 +1245,7 @@ expand_compare_loop (rtx operands[])
do_ifelse (GET_MODE (dcond), NE, NULL_RTX, NULL_RTX,
dcond, diff_label, profile_probability::unlikely ());
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later. */
rtx cmp = gen_rtx_COMPARE (CCUNSmode, d1_2, d2_2);
@@ -1279,7 +1279,7 @@ expand_compare_loop (rtx operands[])
/* If diff is nonzero, branch to difference handling
code. If we exit here with a nonzero diff, it is
because the second word differed. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
do_ifelse (CCUNSmode, NE, NULL_RTX, NULL_RTX, dcond,
diff_label, profile_probability::unlikely ());
else
@@ -1351,7 +1351,7 @@ expand_compare_loop (rtx operands[])
src2_addr, orig_src2);
/* Compare the word, see if we need to do the last partial. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later. */
rtx cmp = gen_rtx_COMPARE (CCUNSmode, d1_1, d2_1);
@@ -1567,7 +1567,7 @@ expand_compare_loop (rtx operands[])
cmpld A,B
setb r */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
emit_insn (gen_setb_unsigned (target, dcond));
else
{
@@ -1874,7 +1874,7 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes,
unsigned int base_align,
/* Compare to zero and branch to convert_label if not zero. */
rtx cvt_ref = gen_rtx_LABEL_REF (VOIDmode, convert_label);
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
/* Generate a compare, and convert with a setb later.
Use cond that is passed in because the caller needs
@@ -1909,7 +1909,7 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes,
unsigned int base_align,
{
/* Just do the subtract/compare. Since this is the last block
the convert code will be generated immediately following. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
rtx cmp = gen_rtx_COMPARE (CCUNSmode, tmp_reg_src1,
tmp_reg_src2);
@@ -1957,7 +1957,7 @@ expand_block_compare (rtx operands[])
but setb works well on P9. */
if (TARGET_32BIT
&& TARGET_POWERPC64
- && !TARGET_P9_MISC)
+ && !TARGET_POWER9)
return false;
/* Allow this param to shut off all expansion. */
@@ -1997,7 +1997,7 @@ expand_block_compare (rtx operands[])
/* P7/P8 code uses cond for subfc. but P9 uses
it for cmpld which needs CCUNSmode. */
rtx cond = NULL;
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
cond = gen_reg_rtx (CCUNSmode);
/* Is it OK to use vec/vsx for this. TARGET_VSX means we have at
@@ -2069,7 +2069,7 @@ expand_block_compare (rtx operands[])
{
if (convert_label)
emit_label (convert_label);
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
emit_insn (gen_setb_unsigned (target, cond));
else
generate_6432_conversion(target, sub_result);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 440b76140bfc..fe17ccf668ca 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3897,7 +3897,7 @@ rs6000_option_override_internal (bool global_init_p)
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+ if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_POWER9)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -24498,7 +24498,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
- { "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1d63d5f1ca38..42213d998133 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -558,6 +558,8 @@ extern int rs6000_vector_align[];
/* ISA bits that are set via -mcpu=<xxx>, but that do not have an associated
switch with the option. */
+#define TARGET_POWER9 \
+ ((rs6000_cpu_option_flags & CPU_OPTION_POWER9_MASK) != 0)
#define TARGET_POWER10 \
((rs6000_cpu_option_flags & CPU_OPTION_POWER10_MASK) != 0)
#define TARGET_POWER11 \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 04a6c0f7461d..a78e1118f50d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6523,7 +6523,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
UNSPECV_MFFSCRN))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"mffscrn %0,%1"
[(set_attr "type" "fp")])
@@ -6531,7 +6531,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(match_operand:SI 1 "const_0_to_3_operand" "n")]
UNSPECV_MFFSCRN))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"mffscrni %0,%1"
[(set_attr "type" "fp")])
@@ -6539,7 +6539,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSCDRN))
(use (match_operand:DF 1 "gpc_reg_operand" "d"))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"mffscdrn %0,%1"
[(set_attr "type" "fp")])
@@ -6552,7 +6552,7 @@
/* The floating point rounding control bits are FPSCR[62:63]. Put the
new rounding mode bits from operands[0][62:63] into FPSCR[62:63]. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
if (const_0_to_3_operand (operands[1], VOIDmode))
emit_insn (gen_rs6000_mffscrni (tmp_df, operands[1]));
@@ -6625,7 +6625,7 @@
/* The decimal floating point rounding control bits are FPSCR[29:31]. Put the
new rounding mode bits from operands[0][61:63] into FPSCR[29:31]. */
- if (TARGET_P9_MISC)
+ if (TARGET_POWER9)
{
rtx src_df = gen_reg_rtx (DFmode);
@@ -14654,7 +14654,7 @@
otherwise fall back to the older mffs instruction to emulate the mffsl
instruction. */
- if (!TARGET_P9_MISC)
+ if (!TARGET_POWER9)
{
rtx tmp1 = gen_reg_rtx (DFmode);
@@ -15609,7 +15609,7 @@
(define_expand "darn_32_<mode>"
[(use (match_operand:GPR 0 "register_operand"))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
emit_insn (gen_darn (<MODE>mode, operands[0], const0_rtx));
DONE;
@@ -15617,7 +15617,7 @@
(define_expand "darn_64_<mode>"
[(use (match_operand:GPR 0 "register_operand"))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
emit_insn (gen_darn (<MODE>mode, operands[0], const1_rtx));
DONE;
@@ -15625,7 +15625,7 @@
(define_expand "darn_raw_<mode>"
[(use (match_operand:GPR 0 "register_operand"))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
emit_insn (gen_darn (<MODE>mode, operands[0], const2_rtx));
DONE;
@@ -15635,7 +15635,7 @@
[(set (match_operand:GPR 0 "register_operand" "=r")
(unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")]
UNSPECV_DARN))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"darn %0,%1"
[(set_attr "type" "integer")])
@@ -15669,7 +15669,7 @@
(const_int 0))
(const_int 1)
(const_int 0))))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
operands[3] = gen_reg_rtx (CCmode);
})
@@ -15688,7 +15688,7 @@
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")]
UNSPEC_CMPRB))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"cmprb %0,0,%1,%2"
[(set_attr "type" "logical")])
@@ -15707,7 +15707,7 @@
(const_int 0))
(const_int 1)
(const_int 0))))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"setb %0,%1"
[(set_attr "type" "logical")])
@@ -15720,7 +15720,7 @@
(const_int 0))
(const_int 1)
(const_int 0))))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"setb %0,%1"
[(set_attr "type" "logical")])
@@ -15755,7 +15755,7 @@
(const_int 0))
(const_int 1)
(const_int 0))))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
{
operands[3] = gen_reg_rtx (CCmode);
})
@@ -15775,7 +15775,7 @@
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")]
UNSPEC_CMPRB2))]
- "TARGET_P9_MISC"
+ "TARGET_POWER9"
"cmprb %0,1,%1,%2"
[(set_attr "type" "logical")])
@@ -15811,7 +15811,7 @@
(const_int 0))
(const_int 1)
(const_int 0))))]
- "TARGET_P9_MISC && TARGET_64BIT"
+ "TARGET_POWER9 && TARGET_64BIT"
{
operands[3] = gen_reg_rtx (CCmode);
})
@@ -15831,7 +15831,7 @@
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_CMPEQB))]
- "TARGET_P9_MISC && TARGET_64BIT"
+ "TARGET_POWER9 && TARGET_64BIT"
"cmpeqb %0,%1,%2"
[(set_attr "type" "logical")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 451afabe2c1f..55590c5fe9dd 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -535,8 +535,7 @@ Target Undocumented Var(unroll_only_small_loops) Init(0)
Save
; Use conservative small loop unrolling.
mpower9-misc
-Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags)
-Use certain scalar instructions added in ISA 3.0.
+Target Undocumented WarnRemoved
mpower9-vector
Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags) WarnRemoved
