The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
eb150f1a07f3... Fix latent LRA bug
It previously pointed to:
eadbcb5cf138... [RISC-V] Adjust recently added test
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
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eadbcb5... [RISC-V] Adjust recently added test
f6d122d... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
53ccfed... RISC-V: Allow errors to be suppressed when parsing architec
79e8e8d... RISC-V: Adjust the vmacc.vx combine test cases
c1d6b61... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
3f7764a... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
4da96ed... RISC-V: Check if we can vec_extract [PR121510].
f4547a1... RISC-V: Use correct target in expand_vec_perm [PR121780].
22c2d4f... RISC-V: Always register vector built-in functions during LT
0d0e5fb... RISC-V: Fix extension subset check in riscv_can_inline_p
6643651... RISC-V: Add support for the XAndesbfhcvt ISA extension.
1ea2e0d... RISC-V: Add support for the XAndesperf ISA extension.
cf4a2ac... RISC-V: Add basic XAndes vendor extension support.
797405e... RISC-V: Add pattern for vector-scalar floating-point max
4d8dc15... [RISC-V][PR target/121213] Avoid unnecessary sign extension
7f834df... RISC-V: Fix is_vlmax_len_p and use for strided ops.
fc2b1f0... RISC-V: Handle overlap in expand_vec_perm PR121742.
cca47d2... RISC-V: Add Zbb extension sext testcase.
2a1bc60... RISC-V: Update Zba 'shNadd.uw' testcase.`
11f33c1... RISC-V: Remove unused print_ext_doc_entry function [NFC]
fbde688... [RISC-V] Improve initial RTL generation for SImode adds on
b5088dd... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
0dd3a3f... RISC-V: Add patterns for vector-scalar IEEE floating-point
cb82060... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
a9a2a3a... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
01ee199... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
2d4b37d... RISC-V: Add pattern for vector-scalar floating-point min
f2a4ace... Remove xfail marker on RISC-V test
e59458c... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
17c97be... More RISC-V testsuite hygiene
992c9ab... [committed] RISC-V Testsuite hygiene
775db99... [PATCH] RISC-V: Add pattern for reverse floating-point divi
44de503... [PATCH] RISC-V: Add pattern for vector-scalar single-width
6980504... Fix RISC-V bootstrap
73c0fd7... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
abca152... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
e88f6f7... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
f9c494f... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
9c276d4... Fix invalid right shift count with recent ifcvt changes
522d3cc... [PR rtl-optimization/120553] Improve selecting between cons
df5e647... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
de678fd... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
a4152fe... [PR target/121213] Avoid unnecessary constant load in amosw
a616a81... regrename: treat writes as reads for fused instruction pair
ec36252... ira: tie output allocnos for fused instruction pairs
535eab3... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
094b2c9... RISC-V: Update the comments of vx combine [NFC]
a88e566... RISC-V: Add missed DONE for vx combine pattern [NFC]
75bb3da... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
52fcaee... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
9dafaad... [RISC-V][PR target/121531] Cover missing insn types in p400
9e19bb5... [RISC-V][PR target/121160] Avoid bogus force_reg call
24a34c6... [RISC-V][PR target/121113] Handle HFmode in various insn re
d1378fc... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
bc3612c... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
146cb77... RISC-V: Expand const_vector with 2 elts per pattern.
dc031c3... Improve initial code generation for addsi/adddi
b04f0b7... Don't run tests requiring "B" on designs without "B"
eeafb85... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
7122e4b... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
c89ae56... RISC-V: Read extension data from riscv-ext*.def for arch-ca
3a68d82... RISC-V: Support -march=unset
b7a23f1... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
b9128d2... RISC-V: Add testcases for signed avg ceil vx combine
909ab3c... RISC-V: Adding H to the canonical order [PR121312]
38da7a8... RISC-V: Add testcases for unsigned avg ceil vx combine.
29d6dce... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
1f6cdea... RISC-V: Remove use of structured binding to fix compiler wa
5b393ab... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
95d2106... RISC-V: Add test case for vaadd.vx combine polluting VXRM
80f7bab... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
17ecffc... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
d247cc6... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
b8b9747... RISC-V: Fix another vf FP16 combine run test failures
66befaf... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
ba96384... RISC-V: Prepare dynamic LMUL heuristic for SLP.
c035faf... RISC-V: Remove user-level interrupts
2fecd9c... RISC-V: Add support for resumable non-maskable interrupt (R
2f5fe11... riscv: testsuite: Fix misalignment check.
300a60f... RISC-V: Add test case for vx combine polluting VXRM
cc8383e... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
17e384f... RISC-V: Rework broadcast handling [PR121073].
05441fa... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
14b823b... Change bellow in comments to below
ba4ff87... [RISC-V] Restrict generic-vector-ooo DFA
652208f... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
c2dda28... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
b14f079... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
085bd57... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
f9f9588... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
7095440... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
8c6025f... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
bf8d760... RISC-V: Refine the test case for vector avg_floor and avg_c
f22c906... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
546656c... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
f7e449b... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
685e0a6... RISC-V: Support RVVDImode for avg3_ceil auto vect
92865e0... RISC-V: Fix vsetvl merge rule.
6761404... RISC-V: Refine the scalar SAT_* test cases
e98582d... RISC-V: Support RVVDImode for avg3_floor auto vect
c2f5b98... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
f5252f9... RISC-V: Add testcase for rv32 SAT_MUL from uint64
dec7adb... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
454ad6a... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
de1c3f5... RISC-V: Make zero-stride load broadcast a tunable.
e632f11... [RISC-V] Detect new fusions for RISC-V
d731163... RISCV: Remove the v extension requirement for sat scalar ru
fcef05f... RISC-V: Add test for vec_duplicate + vssub.vv combine case
c3b011b... RISC-V: Add test for vec_duplicate + vssub.vv combine case
5b43991... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
3ef03de... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
c5289e2... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
309d552... [RISC-V][PR target/120642] Avoid propagating constant AVL f
1ce0e52... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
4b5b7a9... RISC-V: Do not use vsetivli for THeadVector.
951fb6c... RISC-V: Ignore non-types in builtin function hash.
a8ef5fb... [committed][RISC-V] Fix testsuite fallout from check-functi
dc190f0... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
0343884... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
22789db... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
e6d7e19... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
994c0ef... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
810386f... [RISC-V] Add basic instrumentation to fusion detection
75f9379... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
fd1a89c... Refactor record_function_versions.
0c5cbde... [RISC-V][PR target/118886] Refine when two insns are signal
894428e... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
d81f703... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
1739031... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
8a4ed72... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
6e5fef8... RISC-V: Reconcile the existing test due to cost model chang
0e88a9e... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
28760d4... RISC-V: Ignore -Oz for most rvv testcase [NFC]
b1e6ae0... RISC-V: Primary vector pipeline model for sifive 7 series
b3198a1... RISC-V: Adding B ext, fp16 and missing scalar instruction t
e621e7c... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
b9fd723... RISC-V: Refactor the function bitmap_union_of_preds_with_en
e7d112e... RISC-V: Add pipeline-checker script
10b5a47... [RISC-V][PR target/119971] Avoid losing shift count masking
c53a073... RISC-V: update prepare_ternary_operands to handle vector-sc
7ae8653... RISC-V: Fix build issue
8b6db60... RISC-V: Add comment and reorder the the include files in ri
43656c2... RISC-V: Add Profiles RVA/B23S64 support.
b5c8a47... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
7e4c07d... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
cebc0b8... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
9f8311f... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
214a003... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
bd9a322... RISC-V: Fix ICE for expand_select_vldi [PR120652]
66914b8... [RISC-V] Force several tests to use rocket tuning
3408c68... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
dec64c8... RISC-V: Add test for vec_duplicate + vminu.vv combine case
081fc28... RISC-V: Add test for vec_duplicate + vminu.vv combine case
b5ab168... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
97194b3... RISC-V: Add generic tune as default.
4646536... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
9bb75d7... RISC-V: Adding cost model for zilsd
55dd253... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
e45ea74... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
a163fce... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
9d47de9... [PATCH v1] RISC-V: Use scratch reg for loop control
8d14048... RISC-V: Add -fno-pie flags to testcases
ae5b054... RISC-V: Refine VX combine test case 0 to avoid code duplica
0deb969... RISC-V: Update Profiles string in RV23.
da6f8a5... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
b719701... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
6ffaee2... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
22df568... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
662a926... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
d115490... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
8a10ab2... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
7643da9... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
da62f55... RISC-V: Prevent speculative vsetvl insn scheduling
3d45646... RISC-V: Add patterns for vector-scalar negate-(multiply-add
1ac57c0... RISC-V: testsuite: fix an obvious build error
27f9af1... RISC-V: Regen riscv-ext.texi [NFC]
391daf5... RISC-V: Add test for vec_duplicate + vremu.vv combine case
c2c0ece... RISC-V: Add test for vec_duplicate + vremu.vv combine case
5f5bfc5... RISC-V: Reconcile the existing test for vremu.vx combine
d609ccd... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
941c3b6... [RISC-V] Enable more if-conversion on RISC-V
a5251de... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
c4f00c0... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
d573b74... RISC-V: Reconcile the existing test for vrem.vx combine
45a8532... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
1e4f4e9... RISC-V: frm/mode-switch: robustify call_insn backtracking [
bdc0404... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
1a66fa0... RISC-V: frm/mode-switch: remove dubious frm edge insertion
5b65b61... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
9054239... [RISC-V] Handle 32bit operands in condition for conditional
b41bbf1... [to-be-committed][RISC-V] Handle 32bit operands in conditio
9a87f31... RISC-V: Reconcile the existing test for vdivu.vx combine
ecfe214... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
c9dc3a9... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
70c071a... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
be55f31... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
2aad5ee... [RISC-V] Improve signed division by 2^n
29b74ce... RISC-V: Don't use structured binding in riscv-common.cc
c97d8f0... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
a8eee56... [RISC-V] Improve sequences to generate -1, 1 in some cases.
fba637b... RISC-V: Support Ssu64xl extension.
5233572... RISC-V: Support Sstvecd extension.
ae427a9... RISC-V: Support Sstvala extension.
0e9d206... RISC-V: Support Sscounterenw extension.
5e82cda... RISC-V: Support Ssccptr extension.
831aee1... RISC-V: Support Smrnmi extension.
689848b... RISC-V: Support Sm/scsrind extensions.
389f8af... RISC-V: Update extension defination.
9fffa33... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
8e5fde0... [PATCH v2] RISC-V: Add svbare extension.
9c3559b... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
c1b5a3b... RISC-V: Add Shlcofideleg extension.
75bd11c... RISC-V: Reconcile the existing test for vdiv.vx combine
a8df3d9... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
6cc5e74... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
9874af8... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
861d771... RISC-V: Use helper function to get FPR to VR move cost
6fdf007... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
9f9e94c... [PATCH] RISC-V: Add smcntrpmf extension.
68b8a31... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
154f995... RISC-V: Implement full-featured iterator for riscv_subset_l
bc30c55... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
f8dc9ea... RISC-V: Fix line too long format issue for autovect.md [NFC
acf50bd... RISC-V: Add test cases for avg_ceil vaadd implementation
82bcf0e... RISC-V: Reconcile the existing test for avg_ceil
14401c7... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
fd267ab... RISC-V: Add minimal support of double trap extension 1.0
3587175... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
2de45c4... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
55cdeb4... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
c0808d2... RISC-V: Avoid division by zero in check_builtin_call [PR120
fb64082... RISC-V: Add test cases for avg_floor vaadd implementation
557f46c... RISC-V: Reconcile the existing test for avg_floor
b9a3cf3... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
d42c7e1... [RISC-V] Add andi+bclr synthesis
a924f0b... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
7c33483... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
3c6fad5... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
e7d8c57... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
81fa650... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
0e29872... [RISC-V] shift+and+shift for logical and synthesis
5e67cb6... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
c4b6346... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
0223219... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
94fa265... RISC-V: Support CPUs in -march.
769ce60... RISC-V: Add autovec mode param.
3276e62... RISC-V: Default-initialize variable.
d6273b2... RISC-V: Fix some dynamic LMUL costing.
9c333b6... [RISC-V] Clear both upper and lower bits using 3 shifts
c8e443f... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
138d672... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
4dfe4f4... [RISC-V] Clear high or low bits using shift pairs
a33dce9... [RISC-V] Improve (x << C1) + C2 split code
f77092e... [RISC-V][PR target/120368] Fix 32bit shift on rv64
d52017d... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
f15c1ff... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
32b5499... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
ef1fd8f... [RISC-V] Infrastructure of synthesizing logical AND with co
1661042... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
7ca19f9... [PATCH v2 1/2] The following changes enable P8700 processor
e601fc5... [RISC-V] Avoid multiple assignments to output object
2d5625a... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
362e074... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
7cd4255... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a3a18ae... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
bf7d085... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
b026d14... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
60b530a... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
4143f4f... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
91e283e... [committed][RISC-V][PR target/120333] Remove bogus bext pat
5723435... [RISC-V] Fix false positive from Wuninitialized
540a1db... RISC-V: Fix the warning of temporary object dangling refere
666a35c... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
857b771... RISC-V: Support Zilsd code gen
94b41ed... RISC-V: Add new operand constraint: cR
e0fab58... [RISC-V] Fix ICE due to bogus use of gen_rtvec
ba00c04... [RISC-V] Avoid setting output object more than once in IOR/
64f4191... RISC-V: Since the loop increment i++ is unreachable, the lo
377e19c... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
a0a6d75... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
ba41897... Make end_sequence return the insn sequence
d6a1604... RISC-V: Reuse test name for vx combine test data [NFC]
5aa7e5b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
73f6415... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
0202b20... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
d2760b8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
cefa94f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
fe36cc6... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
db3b2ff... RISC-V: Adjust vx combine test case to avoid name conflict
8bb8463... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
8859643... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
99473f3... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
ae1f96f... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
5c9c74c... RISC-V: Add augmented hypervisor series extensions.
dfe5d9b... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
6675d30... RISC-V: Regen riscv-ext.opt.urls
8a2f1af... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
f9ccad6... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
745d492... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
18a6b92... RISC-V: Introduce riscv_ext_info_t to hold extension metada
e081eb6... RISC-V: Adjust riscv_can_inline_p
bd4ece0... RISC-V: Generate extension table in documentation from risc
6dd0b13... RISC-V: Use riscv-ext.def to generate target options and va
88e53e1... RISC-V: Introduce riscv-ext*.def to define extensions
e2d87e9... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
0fd464c... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
a61da66... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
454f68c... RISC-V: Support for zilsd and zclsd extensions.
8a7a24b... testsuite: Fix RISC-V arch-52.c format issue.
bf80965... RISC-V: Support RISC-V Profiles 23.
acc79c4... RISC-V: Support RISC-V Profiles 20/22.
3618348... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
646e491... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
5c8d659... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
08161d0... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
095d892... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
8b149fb... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
745d7d7... RISC-V: Separate the test running of rvv vx_vf
135b18e... [RISC-V][PR target/120137][PR target/120154] Don't create o
1f20e2e... [PATCH] RISC-V: Minimal support for zama16b extension.
08824bb... [RISC-V] Avoid unnecessary andi with -1 argument
77d826d... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
ecb9dac... [PATCH] RISC-V: Recognized svadu and svade extension
5421721... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
9e073f6... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
ac1c823... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
3ebd71a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
6575e8a... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
3435168... RISC-V: Add gr2vr cost helper function
7dfaf70... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
1994653... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
395cffc... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
e4ec1d3... [V2][RISC-V] Trivial permutation constant derivation
dc6ef96... [RISC-V] Adjust rvv tests after recent jump threading chang
7771742... [PATCH] RISC-V: Implment H modifier for printing the next r
d751483... [to-be-committed][RISC-V] Adjust testcases and finish regis
e493d49... RISC-V: Remove unnecessary frm restore volatile define_insn
de828d5... RISC-V: Allow different dynamic floating point mode to be m
2df4cd7... RISC-V: Fix missing implied Zicsr from Zve32x
6703471... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
e44b404... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
58f6b84... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
2ea8cc2... RISC-V: Extract vector stepped for expand_const_vector [NFC
cda6c6e... RISC-V: Extract vector duplicate for expand_const_vector [N
16b845b... RISC-V: Extract vec_series for expand_const_vector [NFC]
afd28fe... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
24cfcc1... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
52989e4... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
2844769... [riscv] vec_dup immediate constants in pred_broadcast expan
1976244... [RISC-V][PR target/119865] Don't free ggc allocated memory
ffefe78... [RISC-V][PR target/118410] Improve code generation for some
79ae019... [RISC-V] Fix missed bext discovery
786bfe2... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
f4f0e5d... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
d7a046f... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
eb150f1... Fix latent LRA bug
3cff286... RISC-V: Support vnclip idiom testcase [PR120378]
df708cb... Match: Support SAT_TRUNC variant NARROW_CLIP
f667087... [RISC-V] Adjust ABI specification in recently added Andes t
074e09c... RISC-V: Suppress cross CC sibcall optimization from vector
7ab6db6... RISC-V: Add min/max patterns for ifcvt.
18ef461... ifcvt: Clarify if_info.original_cost.
8d2c2f1... RISC-V: Fix can_find_related_mode_p for VLS types
0ce2bb9... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
8a5b972... RISC-V: Add pattern for vector-scalar single widening float
902064d... RISC-V: Add pattern for vector-scalar dual widening floatin
e1015d1... RISC-V: Add pattern for vector-scalar single widening float
e386a02... RISC-V: Add pattern for vector-scalar widening floating-poi
d2fb01e... RISC-V: Adjust tt-ascalon-d8 branch cost
6a30568... RISC-V: Add pattern for vector-scalar single-width floating
c98cdf0... RISC-V: Add pattern for vector-scalar single-width floating
4405f45... RISC-V: Add pattern for vector-scalar single-width floating
8b5fd4a... RISC-V: Add pattern for vector-scalar widening floating-poi
ed329bd... RISC-V: Add patterns for vector-scalar IEEE floating-point
43c740c... gcc: introduce the dep_fusion pass
ff229c4... RISC-V: Add support for the XAndesvdot ISA extension.
a15da95... [RISC-V] Fix ordering of pipeline models
9d7df5e... RISC-V: Add support for the XAndesvpackfph ISA extension.
b6c74f5... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
268cd08... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
28bdf2d... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
268c33d... dep_fusion: Fix if target does not have macro fusion [PR121
d42f020... gcc: introduce the dep_fusion pass
9d2433d... RISC-V: Add support for the XAndesvsintload ISA extension.
85a9f5d... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
ea75e24... RISC-V: Add tt-ascalon-d8 pipeline description
7d822b5... [RISC-V] Adjust recently added test
dfe99cc... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
a53e328... RISC-V: Allow errors to be suppressed when parsing architec
a051078... RISC-V: Adjust the vmacc.vx combine test cases
8596562... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
0dbb2be... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
0fa5b5b... RISC-V: Use correct target in expand_vec_perm [PR121780].
94e902f... RISC-V: Always register vector built-in functions during LT
aeb3508... RISC-V: Fix extension subset check in riscv_can_inline_p
104ddd6... RISC-V: Add support for the XAndesbfhcvt ISA extension.
31b8d5c... RISC-V: Add support for the XAndesperf ISA extension.
e537a2a... RISC-V: Add basic XAndes vendor extension support.
f58e67e... RISC-V: Add pattern for vector-scalar floating-point max
d64f510... [RISC-V][PR target/121213] Avoid unnecessary sign extension
72be713... RISC-V: Fix is_vlmax_len_p and use for strided ops.
d4a5d8d... RISC-V: Handle overlap in expand_vec_perm PR121742.
99fdaa3... RISC-V: Add Zbb extension sext testcase.
2c89d44... RISC-V: Update Zba 'shNadd.uw' testcase.`
847f878... RISC-V: Remove unused print_ext_doc_entry function [NFC]
cef6a88... [RISC-V] Improve initial RTL generation for SImode adds on
8986a67... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
8d15c1c... RISC-V: Add patterns for vector-scalar IEEE floating-point
f356439... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
3ce39b5... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
79f538e... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
361aa8a... RISC-V: Add pattern for vector-scalar floating-point min
8ac6795... Remove xfail marker on RISC-V test
db540fc... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
25fd42d... More RISC-V testsuite hygiene
41c322c... [committed] RISC-V Testsuite hygiene
57a554e... [PATCH] RISC-V: Add pattern for reverse floating-point divi
06cef8c... [PATCH] RISC-V: Add pattern for vector-scalar single-width
d5c2c56... Fix RISC-V bootstrap
e91a6ef... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
4ad94f9... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
6462c2b... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
207f3a0... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
778fa3c... Fix invalid right shift count with recent ifcvt changes
dd31e96... [PR rtl-optimization/120553] Improve selecting between cons
5ae9896... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
9039453... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
580cd2f... [PR target/121213] Avoid unnecessary constant load in amosw
52908a9... regrename: treat writes as reads for fused instruction pair
a3c303d... ira: tie output allocnos for fused instruction pairs
3500479... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
ad4ac3a... RISC-V: Update the comments of vx combine [NFC]
d7f81bc... RISC-V: Add missed DONE for vx combine pattern [NFC]
87299ec... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
97fa0ab... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
7eb565a... [RISC-V][PR target/121531] Cover missing insn types in p400
bea502e... [RISC-V][PR target/121160] Avoid bogus force_reg call
578b687... [RISC-V][PR target/121113] Handle HFmode in various insn re
652f761... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
c4a2f91... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
e8ade79... RISC-V: Expand const_vector with 2 elts per pattern.
bfbe3e2... Improve initial code generation for addsi/adddi
a680633... Don't run tests requiring "B" on designs without "B"
f2e85de... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
01e5068... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
2886eee... RISC-V: Read extension data from riscv-ext*.def for arch-ca
fb5cc25... RISC-V: Support -march=unset
c4b6960... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
893783a... RISC-V: Add testcases for signed avg ceil vx combine
7212548... RISC-V: Adding H to the canonical order [PR121312]
295de2b... RISC-V: Add testcases for unsigned avg ceil vx combine.
6de1b95... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
2004f04... RISC-V: Remove use of structured binding to fix compiler wa
ef80db6... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
c56d054... RISC-V: Add test case for vaadd.vx combine polluting VXRM
5ab446e... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
2f106c8... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
f0cb00f... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
fe3c30c... RISC-V: Fix another vf FP16 combine run test failures
9ecef70... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
7614ace... RISC-V: Prepare dynamic LMUL heuristic for SLP.
2425ba0... RISC-V: Remove user-level interrupts
2f60948... RISC-V: Add support for resumable non-maskable interrupt (R
cce3932... riscv: testsuite: Fix misalignment check.
b5208ba... RISC-V: Add test case for vx combine polluting VXRM
25a1f1c... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
f8aecfa... RISC-V: Rework broadcast handling [PR121073].
72792ff... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
481930e... Change bellow in comments to below
6acf236... [RISC-V] Restrict generic-vector-ooo DFA
a142db0... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
cb58cee... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
3801ce3... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
8ad7351... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
db2be63... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
1180dc9... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
da34ac6... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
fe560be... RISC-V: Refine the test case for vector avg_floor and avg_c
b5c8d2c... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
c1c5a14... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
83f4ccc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
4a64dc5... RISC-V: Support RVVDImode for avg3_ceil auto vect
201f84e... RISC-V: Fix vsetvl merge rule.
b51791e... RISC-V: Refine the scalar SAT_* test cases
87b354e... RISC-V: Support RVVDImode for avg3_floor auto vect
cd70128... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
33927e2... RISC-V: Add testcase for rv32 SAT_MUL from uint64
5bd4d8f... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
65c1a52... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
7a0843f... RISC-V: Make zero-stride load broadcast a tunable.
88c7db0... [RISC-V] Detect new fusions for RISC-V
0359291... RISCV: Remove the v extension requirement for sat scalar ru
78f75ae... RISC-V: Add test for vec_duplicate + vssub.vv combine case
cf44911... RISC-V: Add test for vec_duplicate + vssub.vv combine case
39b976b... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
2fae7fb... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
474878a... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
c4a4fc2... [RISC-V][PR target/120642] Avoid propagating constant AVL f
7fec806... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
a051974... RISC-V: Do not use vsetivli for THeadVector.
f1e49af... RISC-V: Ignore non-types in builtin function hash.
5eef4d4... [committed][RISC-V] Fix testsuite fallout from check-functi
5ff0fa8... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
7f7cfac... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
9f54e4a... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
68c9a44... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
24e2641... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
67e71a6... [RISC-V] Add basic instrumentation to fusion detection
38a324f... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
f158bcd... Refactor record_function_versions.
6025fc8... [RISC-V][PR target/118886] Refine when two insns are signal
701108e... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
f11124f... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
d0ad00f... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
88bb8a1... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
1dea554... RISC-V: Reconcile the existing test due to cost model chang
10c230a... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
a141780... RISC-V: Ignore -Oz for most rvv testcase [NFC]
a1a50b7... RISC-V: Primary vector pipeline model for sifive 7 series
05aa239... RISC-V: Adding B ext, fp16 and missing scalar instruction t
c196968... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
dfeac1a... RISC-V: Refactor the function bitmap_union_of_preds_with_en
6391d9c... RISC-V: Add pipeline-checker script
2db5155... [RISC-V][PR target/119971] Avoid losing shift count masking
eeae027... RISC-V: update prepare_ternary_operands to handle vector-sc
cc4fb3d... RISC-V: Fix build issue
c2dbb6f... RISC-V: Add comment and reorder the the include files in ri
e5839aa... RISC-V: Add Profiles RVA/B23S64 support.
9cc8b2f... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
1908d07... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
31c1453... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
f6a7400... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
9790216... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
0708ff5... RISC-V: Fix ICE for expand_select_vldi [PR120652]
22cd180... [RISC-V] Force several tests to use rocket tuning
540833e... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
8b010c6... RISC-V: Add test for vec_duplicate + vminu.vv combine case
78fafe5... RISC-V: Add test for vec_duplicate + vminu.vv combine case
67cbecb... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
f058ab9... RISC-V: Add generic tune as default.
ce6cc7d... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
8831a31... RISC-V: Adding cost model for zilsd
ca1bd59... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
ef720a8... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
7822896... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
54c7cce... [PATCH v1] RISC-V: Use scratch reg for loop control
23e97c4... RISC-V: Add -fno-pie flags to testcases
a769777... RISC-V: Refine VX combine test case 0 to avoid code duplica
3f10401... RISC-V: Update Profiles string in RV23.
77daa1d... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
9bdce6a... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
79a830c... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
100225f... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
33ba9ce... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
2f36a39... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
e432c75... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
57605a0... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
b81a42d... RISC-V: Prevent speculative vsetvl insn scheduling
9b9f51a... RISC-V: Add patterns for vector-scalar negate-(multiply-add
bcc6f4d... RISC-V: testsuite: fix an obvious build error
da17e1a... RISC-V: Regen riscv-ext.texi [NFC]
4dc4609... RISC-V: Add test for vec_duplicate + vremu.vv combine case
b7fcd19... RISC-V: Add test for vec_duplicate + vremu.vv combine case
9f12259... RISC-V: Reconcile the existing test for vremu.vx combine
f8735a7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
cd4527f... [RISC-V] Enable more if-conversion on RISC-V
ffc1e5f... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
e517ecc... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
75e94f9... RISC-V: Reconcile the existing test for vrem.vx combine
fc92dba... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
a28e5e9... RISC-V: frm/mode-switch: robustify call_insn backtracking [
d901e45... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
c9ffb42... RISC-V: frm/mode-switch: remove dubious frm edge insertion
90e4cf3... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
6d8659f... [RISC-V] Handle 32bit operands in condition for conditional
0c20acf... [to-be-committed][RISC-V] Handle 32bit operands in conditio
2babc25... RISC-V: Reconcile the existing test for vdivu.vx combine
06989c6... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
8b34fd6... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
00dfa94... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
1b14356... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
6d50409... [RISC-V] Improve signed division by 2^n
db0fd05... RISC-V: Don't use structured binding in riscv-common.cc
9d4fbe2... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
3f414c7... [RISC-V] Improve sequences to generate -1, 1 in some cases.
cac514f... RISC-V: Support Ssu64xl extension.
d4122be... RISC-V: Support Sstvecd extension.
a19daf1... RISC-V: Support Sstvala extension.
f1f241c... RISC-V: Support Sscounterenw extension.
32ec9d5... RISC-V: Support Ssccptr extension.
0eb29ee... RISC-V: Support Smrnmi extension.
97dd38d... RISC-V: Support Sm/scsrind extensions.
9fe0b82... RISC-V: Update extension defination.
1fcc389... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
9602b05... [PATCH v2] RISC-V: Add svbare extension.
9c37d40... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
eb0269f... RISC-V: Add Shlcofideleg extension.
d7e7745... RISC-V: Reconcile the existing test for vdiv.vx combine
f17fbff... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
1682561... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
7be061f... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
5143fa4... RISC-V: Use helper function to get FPR to VR move cost
a562773... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
13ecc32... [PATCH] RISC-V: Add smcntrpmf extension.
08dcca3... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
89fef47... RISC-V: Implement full-featured iterator for riscv_subset_l
117afb6... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
7aae85d... RISC-V: Fix line too long format issue for autovect.md [NFC
4c37e89... RISC-V: Add test cases for avg_ceil vaadd implementation
cc1e00a... RISC-V: Reconcile the existing test for avg_ceil
6ff9c6e... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
8e91c55... RISC-V: Add minimal support of double trap extension 1.0
a10973b... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
039c211... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
88ecbc9... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
d39c700... RISC-V: Avoid division by zero in check_builtin_call [PR120
9ee44a0... RISC-V: Add test cases for avg_floor vaadd implementation
4ae3428... RISC-V: Reconcile the existing test for avg_floor
237e6f7... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
81eda40... [RISC-V] Add andi+bclr synthesis
c6a7e11... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
e07c7bf... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
fbe28ca... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
a4b7bcc... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
0cc5036... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
975f447... [RISC-V] shift+and+shift for logical and synthesis
100d029... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
a7b8a3b... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
9b8b257... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
eb8bd08... RISC-V: Support CPUs in -march.
3fef165... RISC-V: Add autovec mode param.
92a2798... RISC-V: Default-initialize variable.
796346e... RISC-V: Fix some dynamic LMUL costing.
60b781c... [RISC-V] Clear both upper and lower bits using 3 shifts
cc441a5... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
9611a54... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
192a7b5... [RISC-V] Clear high or low bits using shift pairs
dbf8782... [RISC-V] Improve (x << C1) + C2 split code
11150f3... [RISC-V][PR target/120368] Fix 32bit shift on rv64
6dee672... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
21d0d9a... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
5b1ded9... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
afd52cc... [RISC-V] Infrastructure of synthesizing logical AND with co
8257509... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
28eefd4... [PATCH v2 1/2] The following changes enable P8700 processor
1d00b29... [RISC-V] Avoid multiple assignments to output object
7c03b3a... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
c2b32db... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
b50fd63... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
cb21a95... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
796989b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
2a0e5c6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
7519537... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
9c9d994... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
5a901b1... [committed][RISC-V][PR target/120333] Remove bogus bext pat
70295d0... [RISC-V] Fix false positive from Wuninitialized
4de5851... RISC-V: Fix the warning of temporary object dangling refere
d43f655... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
02bfc18... RISC-V: Support Zilsd code gen
7854069... RISC-V: Add new operand constraint: cR
1403a25... [RISC-V] Fix ICE due to bogus use of gen_rtvec
c604c4f... [RISC-V] Avoid setting output object more than once in IOR/
4fb180c... RISC-V: Since the loop increment i++ is unreachable, the lo
ac33469... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
eec3a8a... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
dbdc116... Make end_sequence return the insn sequence
441da7e... RISC-V: Reuse test name for vx combine test data [NFC]
bd201c2... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6b31d5... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
2b63862... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
9cb277b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
33e732c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
5cf4aac... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
3970b35... RISC-V: Adjust vx combine test case to avoid name conflict
92dc846... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
55d8883... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
b02bab5... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
97741b4... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
4c43ce7... RISC-V: Add augmented hypervisor series extensions.
7c5bef0... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
20b55d9... RISC-V: Regen riscv-ext.opt.urls
7188430... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
ae541e4... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
c3b7684... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
6791d38... RISC-V: Introduce riscv_ext_info_t to hold extension metada
007dc74... RISC-V: Adjust riscv_can_inline_p
9265ed2... RISC-V: Generate extension table in documentation from risc
2375a31... RISC-V: Use riscv-ext.def to generate target options and va
d826fd8... RISC-V: Introduce riscv-ext*.def to define extensions
f539d0c... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
95e14bf... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
3ddefe7... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
b507680... RISC-V: Support for zilsd and zclsd extensions.
5e925df... testsuite: Fix RISC-V arch-52.c format issue.
da9d35a... RISC-V: Support RISC-V Profiles 23.
3c88742... RISC-V: Support RISC-V Profiles 20/22.
19ca071... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
5f42690... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
0c8f5d9... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
272ea7f... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e05923c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
583ff95... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
0ec8a28... RISC-V: Separate the test running of rvv vx_vf
aec5f9a... [RISC-V][PR target/120137][PR target/120154] Don't create o
c62f976... [PATCH] RISC-V: Minimal support for zama16b extension.
9bd3a6f... [RISC-V] Avoid unnecessary andi with -1 argument
42b7dad... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
7f8e2da... [PATCH] RISC-V: Recognized svadu and svade extension
6846802... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
1c8565a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
ce5cf7e... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
2ceff77... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
988ed28... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
d2f7845... RISC-V: Add gr2vr cost helper function
b535374... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
af726b8... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
c8b0971... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
c43ec17... [V2][RISC-V] Trivial permutation constant derivation
7e41041... [RISC-V] Adjust rvv tests after recent jump threading chang
932cc96... [PATCH] RISC-V: Implment H modifier for printing the next r
33847ab... [to-be-committed][RISC-V] Adjust testcases and finish regis
3e21220... RISC-V: Remove unnecessary frm restore volatile define_insn
48fb726... RISC-V: Allow different dynamic floating point mode to be m
d7b5819... RISC-V: Fix missing implied Zicsr from Zve32x
69d67f1... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
e60a6c0... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
0b7aff4... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
1e94dbc... RISC-V: Extract vector stepped for expand_const_vector [NFC
c9a253d... RISC-V: Extract vector duplicate for expand_const_vector [N
ab1776f... RISC-V: Extract vec_series for expand_const_vector [NFC]
430dbc8... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
39c9a71... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
4f89088... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
08180c3... [riscv] vec_dup immediate constants in pred_broadcast expan
e4e5214... [RISC-V][PR target/119865] Don't free ggc allocated memory
9acc28f... [RISC-V][PR target/118410] Improve code generation for some
aec35ca... [RISC-V] Fix missed bext discovery
3f0700b... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
93b0c20... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
d1f60eb... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
69d54b0... Daily bump. (*)
210b7a0... libstdc++: Fix memory leak in PSTL TBB backend [PR117276] (*)
a03c244... c++: pack indexing is a non-deduced context [PR121795] (*)
6a8999f... Daily bump. (*)
1669dbb... c++: constant non-dep init folding vs FIELD_DECL access [PR (*)
34bc617... rtl-ssa: Maintain clobber_group invariant [PR121757] (*)
b97c46e... ada: Compiler crash on container aggregate association with (*)
1d086cf... ada: Spurious error on generalized prefix notation (*)
cb5abf3... ada: Create a pragma to emit a misplaced Storage_Size aspec (*)
a635f97... ada: Typo fix in comment (*)
59d8156... ada: Reject pragma Attach_Handler on procedures in protecte (*)
03054f9... ada: Fix crash with global No_Tasking and async delays (*)
d64bfa3... ada: Compiler crash on container aggregate with constant el (*)
2cb64a5... ada: Avoid generating incorrect warning (*)
e2dfb46... ada: Minor typo fix in comment (*)
ff0310c... Daily bump. (*)
8844375... libstdc++: Remove blank line from bits/unique_ptr.h (*)
29ef014... AVR: Disable tree-switch-conversion per default. (*)
2bd80c1... Daily bump. (*)
cf5495b... Fortran: fix TRANSFER with rank 1 unlimited polymorphic SOU (*)
afb9ad0... libstdc++: Document remaining C++17 implementation-defined (*)
23109ee... libstdc++: Document missing implementation defined behavior (*)
03d4c0c... Daily bump. (*)
a8aa1cd... libstdc++: Fix docs for --enable-vtable-verify [PR120698] (*)
1c824f0... RISC-V: Check if we can vec_extract [PR121510]. (*)
c5314c9... Daily bump. (*)
bfe3b5b... libphobos: enable for more hppa tuples (*)
d9fbf1d... libphobos: enable for sparc64-unknown-linux-gnu (*)
7312653... AVR: ad target/121794 - Invoke zero_reg less. (*)
f95c1df... libphobos: enable for powerpc64le-linux-gnu (*)
29d96d5... Daily bump. (*)
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