https://gcc.gnu.org/g:2963f5f7bd6db0e3f023fadb4c9c3d9e1a3fdcad
commit r16-3555-g2963f5f7bd6db0e3f023fadb4c9c3d9e1a3fdcad
Author: Kuan-Lin Chen <ru...@andestech.com>
Date: Wed Sep 3 17:03:05 2025 -0600
RISC-V: Add support for the XAndesbfhcvt ISA extension.
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
* config/riscv/riscv.md (truncsfbf2): Add TARGET_XANDESBFHCVT
support.
(extendbfsf2): Ditto.
* config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandes/xandesbfhcvt-1.c: New test.
* gcc.target/riscv/xandes/xandesbfhcvt-2.c: New test.
Diff:
---
gcc/config/riscv/andes.def | 4 ++++
gcc/config/riscv/riscv-builtins.cc | 3 +++
gcc/config/riscv/riscv-ftypes.def | 2 ++
gcc/config/riscv/riscv.md | 18 ++++++++++++++----
gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-1.c | 11 +++++++++++
gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-2.c | 11 +++++++++++
6 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/andes.def b/gcc/config/riscv/andes.def
index e2d67b8b2f18..8345ef6c13be 100644
--- a/gcc/config/riscv/andes.def
+++ b/gcc/config/riscv/andes.def
@@ -8,3 +8,7 @@ RISCV_BUILTIN (nds_ffmismsi, "nds_ffmism_32",
RISCV_BUILTIN_DIRECT, RISCV_SI_FTY
RISCV_BUILTIN (nds_ffmismdi, "nds_ffmism_64", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_UDI_UDI, andesperf64),
RISCV_BUILTIN (nds_flmismsi, "nds_flmism_32", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_USI_USI, andesperf32),
RISCV_BUILTIN (nds_flmismdi, "nds_flmism_64", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_UDI_UDI, andesperf64),
+
+/* Andes Scalar BFLOAT16 Conversion Extension */
+RISCV_BUILTIN_NO_PREFIX (extendbfsf2, "nds_fcvt_s_bf16", RISCV_BUILTIN_DIRECT,
RISCV_SF_FTYPE_BF, andesbfhcvt),
+RISCV_BUILTIN_NO_PREFIX (truncsfbf2, "nds_fcvt_bf16_s", RISCV_BUILTIN_DIRECT,
RISCV_BF_FTYPE_SF, andesbfhcvt),
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index cfcacf40a93b..5d8ff3278e74 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -140,6 +140,7 @@ AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT)
/* ANDES AVAIL. */
AVAIL (andesperf32, !TARGET_64BIT && TARGET_XANDESPERF)
AVAIL (andesperf64, TARGET_64BIT && TARGET_XANDESPERF)
+AVAIL (andesbfhcvt, TARGET_XANDESBFHCVT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -198,6 +199,8 @@ AVAIL (andesperf64, TARGET_64BIT && TARGET_XANDESPERF)
#define RISCV_ATYPE_DI intDI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
+#define RISCV_ATYPE_BF bfloat16_type_node
+#define RISCV_ATYPE_SF float_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def
b/gcc/config/riscv/riscv-ftypes.def
index 6db41adc63ce..9aaea7d3c7e8 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -37,6 +37,8 @@ DEF_RISCV_FTYPE (1, (USI, UQI))
DEF_RISCV_FTYPE (1, (USI, UHI))
DEF_RISCV_FTYPE (1, (SI, QI))
DEF_RISCV_FTYPE (1, (SI, HI))
+DEF_RISCV_FTYPE (1, (BF, SF))
+DEF_RISCV_FTYPE (1, (SF, BF))
DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
DEF_RISCV_FTYPE (2, (USI, USI, UHI))
DEF_RISCV_FTYPE (2, (USI, USI, QI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 63d7daa01b0a..8c7d9aca16c2 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1864,8 +1864,13 @@
[(set (match_operand:BF 0 "register_operand" "=f")
(float_truncate:BF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_ZFBFMIN"
- "fcvt.bf16.s\t%0,%1"
+ "TARGET_ZFBFMIN || TARGET_XANDESBFHCVT"
+{
+ if (TARGET_ZFBFMIN)
+ return "fcvt.bf16.s\t%0,%1";
+ else
+ return "nds.fcvt.bf16.s\t%0,%1";
+}
[(set_attr "type" "fcvt")
(set_attr "mode" "BF")])
@@ -2052,8 +2057,13 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_extend:SF
(match_operand:BF 1 "register_operand" " f")))]
- "TARGET_ZFBFMIN"
- "fcvt.s.bf16\t%0,%1"
+ "TARGET_ZFBFMIN || TARGET_XANDESBFHCVT"
+{
+ if (TARGET_ZFBFMIN)
+ return "fcvt.s.bf16\t%0,%1";
+ else
+ return "nds.fcvt.s.bf16\t%0,%1";
+}
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-1.c
b/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-1.c
new file mode 100644
index 000000000000..e7fc3197d901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xandesbfhcvt -mabi=ilp32" { target { rv32 } } }
*/
+/* { dg-options "-march=rv64gc_xandesbfhcvt -mabi=lp64" { target { rv64 } } }
*/
+
+float
+nds_fcvt_s_bf16 (__bf16 a)
+{
+ return __builtin_riscv_nds_fcvt_s_bf16 (a);
+}
+
+/* { dg-final { scan-assembler-times {nds\.fcvt\.s\.bf16} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-2.c
b/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-2.c
new file mode 100644
index 000000000000..c54bcd4d23a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandesbfhcvt-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xandesbfhcvt -mabi=ilp32" { target { rv32 } } }
*/
+/* { dg-options "-march=rv64gc_xandesbfhcvt -mabi=lp64" { target { rv64 } } }
*/
+
+__bf16
+nds_fcvt_bf16_s (float a)
+{
+ return __builtin_riscv_nds_fcvt_bf16_s (a);
+}
+
+/* { dg-final { scan-assembler-times {nds\.fcvt\.bf16\.s} 1 } } */
