https://gcc.gnu.org/g:52d5fc64a4fa71d78078110bb9fa3d972a743a2a
commit r16-3450-g52d5fc64a4fa71d78078110bb9fa3d972a743a2a
Author: Pan Li <pan2...@intel.com>
Date: Thu Aug 28 10:36:35 2025 +0800
RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR
cost 0, 1 and 15
Add asm dump check and run test for vec_duplicate + vnmsac.vvm
combine to vnmsac.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
for vnmsac.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx_ternary.h | 2 +
.../riscv/rvv/autovec/vx_vf/vx_ternary_data.h | 368 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c | 16 +
.../riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c | 16 +
.../riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c | 16 +
.../riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c | 16 +
18 files changed, 446 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index e99744c037bb..ad2dacd1f25a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 1f1f3d28d135..ebcdb0aeb0f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index f6bbfaea4386..f15d7b552072 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
} } } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index d9fd498bc3da..c9973485e0ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 5ddcc2d0767a..db272ef0f49e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 1b25d79ae55e..b3f99ba7c8b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 71507859bc88..4fdf8f986fd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 077fab91d8c4..02cf934f943f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 056f2c02c6b3..94f83ffe588f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index f36939431d77..77468092cfe9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index bc00c6bc7271..ed31e7965ccb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 15716f682270..b9d1ddc039be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
/* { dg-final { scan-assembler-not {vssub.vx} } } */
/* { dg-final { scan-assembler-not {vaadd.vx} } } */
/* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index be54a3ad33dd..2325c7b86321 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -28,8 +28,10 @@ test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T *
restrict vs2, \
#define TEST_TERNARY_VX_SIGNED_0(T) \
DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \
+ DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \
#define TEST_TERNARY_VX_UNSIGNED_0(T) \
DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \
+ DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
index 8fed997eeb87..9ac1a7ddc3a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -374,4 +374,372 @@ uint64_t TEST_TERNARY_DATA(uint64_t, macc)[][4][N] =
},
};
+int8_t TEST_TERNARY_DATA(int8_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ },
+ },
+ {
+ { 127 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -8, -8, -8, -8,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 127, 127, 127, 127,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -128, -128, -128, -128,
+ },
+ {
+ 127, 127, 127, 127,
+ -125, -125, -125, -125,
+ -8, -8, -8, -8,
+ 126, 126, 126, 126,
+ },
+ },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ },
+ },
+ {
+ { 32767 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -8, -8, -8, -8,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 32767, 32767, 32767, 32767,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -32768, -32768, -32768, -32768,
+ },
+ {
+ 32767, 32767, 32767, 32767,
+ -32765, -32765, -32765, -32765,
+ -8, -8, -8, -8,
+ 32766, 32766, 32766, 32766,
+ },
+ },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ },
+ },
+ {
+ { 2147483647 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -8, -8, -8, -8,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ -2147483645, -2147483645, -2147483645, -2147483645,
+ -8, -8, -8, -8,
+ 2147483646, 2147483646, 2147483646, 2147483646,
+ },
+ },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ },
+ },
+ {
+ { 9223372036854775807ull }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -8, -8, -8, -8,
+ -2, -2, -2, -2,
+ },
+ { /* vd */
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ 2, 2,
2, 2,
+ 0, 0,
0, 0,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ },
+ {
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ -9223372036854775805ull, -9223372036854775805ull,
-9223372036854775805ull, -9223372036854775805ull,
+ -8, -8,
-8, -8,
+ 9223372036854775806ull, 9223372036854775806ull,
9223372036854775806ull, 9223372036854775806ull,
+ },
+ },
+};
+
+uint8_t TEST_TERNARY_DATA(uint8_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 8, 8, 8, 8,
+ 7, 7, 7, 7,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 7, 7, 7, 7,
+ 5, 5, 5, 5,
+ },
+ },
+ {
+ { 128 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 8, 8, 8, 8,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 127, 127, 127, 127,
+ 255, 255, 255, 255,
+ 254, 254, 254, 254,
+ 252, 252, 252, 252,
+ },
+ {
+ 127, 127, 127, 127,
+ 127, 127, 127, 127,
+ 254, 254, 254, 254,
+ 252, 252, 252, 252,
+ },
+ },
+};
+
+uint16_t TEST_TERNARY_DATA(uint16_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 8, 8, 8, 8,
+ 7, 7, 7, 7,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 7, 7, 7, 7,
+ 5, 5, 5, 5,
+ },
+ },
+ {
+ { 32768 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 8, 8, 8, 8,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 32767, 32767, 32767, 32767,
+ 65535, 65535, 65535, 65535,
+ 65534, 65534, 65534, 65534,
+ 65532, 65532, 65532, 65532,
+ },
+ {
+ 32767, 32767, 32767, 32767,
+ 32767, 32767, 32767, 32767,
+ 65534, 65534, 65534, 65534,
+ 65532, 65532, 65532, 65532,
+ },
+ },
+};
+
+uint32_t TEST_TERNARY_DATA(uint32_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 8, 8, 8, 8,
+ 7, 7, 7, 7,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 7, 7, 7, 7,
+ 5, 5, 5, 5,
+ },
+ },
+ {
+ { 2147483648 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 8, 8, 8, 8,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967292, 4294967292, 4294967292, 4294967292,
+ },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967292, 4294967292, 4294967292, 4294967292,
+ },
+ },
+};
+
+uint64_t TEST_TERNARY_DATA(uint64_t, nmsac)[][4][N] =
+{
+ {
+ { 1 }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 8, 8, 8, 8,
+ 7, 7, 7, 7,
+ },
+ {
+ 1, 1, 1, 1,
+ 1, 1, 1, 1,
+ 7, 7, 7, 7,
+ 5, 5, 5, 5,
+ },
+ },
+ {
+ { 9223372036854775808ull }, /* rs1 */
+ { /* vs2 */
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 8, 8, 8, 8,
+ 2, 2, 2, 2,
+ },
+ { /* vd */
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ 18446744073709551615ull, 18446744073709551615ull,
18446744073709551615ull, 18446744073709551615ull,
+ 18446744073709551614ull, 18446744073709551614ull,
18446744073709551614ull, 18446744073709551614ull,
+ 18446744073709551612ull, 18446744073709551612ull,
18446744073709551612ull, 18446744073709551612ull,
+ },
+ {
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
+ 18446744073709551614ull, 18446744073709551614ull,
18446744073709551614ull, 18446744073709551614ull,
+ 18446744073709551612ull, 18446744073709551612ull,
18446744073709551612ull, 18446744073709551612ull,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c
new file mode 100644
index 000000000000..6deee02edfcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T int16_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c
new file mode 100644
index 000000000000..65d376b395e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T int32_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c
new file mode 100644
index 000000000000..832023aa763a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T int64_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c
new file mode 100644
index 000000000000..ae48e2eaf424
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T int8_t
+#define NAME nmsac
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
