https://gcc.gnu.org/g:31a180d8a4c2893e7c4be43e3daaac12347dddb5
commit r16-3441-g31a180d8a4c2893e7c4be43e3daaac12347dddb5
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Wed Aug 27 19:38:15 2025 +0200
RISC-V: Add pattern for vector-scalar floating-point min
This pattern enables the combine pass (or late-combine, depending on the
case)
to merge a vec_duplicate into an smin RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfmin.vv v1,v1,v2
After, we get only one:
vfmin.vf v1,v1,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfmin_vf_<mode>): Add new pattern to
combine vec_duplicate + vfmin.vv into vfmin.vf.
* config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS
modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: Adjust
scan
dump.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmin.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for
function variants.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
vfmin.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c: New test.
Diff:
---
gcc/config/riscv/autovec-opt.md | 19 +++
gcc/config/riscv/vector.md | 24 ++--
.../riscv/rvv/autovec/vls/floating-point-min-2.c | 2 +-
.../riscv/rvv/autovec/vls/floating-point-min-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 5 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 5 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 5 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h | 81 ++++++++++++
.../riscv/rvv/autovec/vx_vf/vf_binop_data.h | 147 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c | 20 +++
.../riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c | 16 +++
.../riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c | 16 +++
18 files changed, 340 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 29bdfc3d90fc..1440eeaea905 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2065,3 +2065,22 @@
}
[(set_attr "type" "vfmuladd")]
)
+
+;; vfmin.vf
+(define_insn_and_split "*vfmin_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (smin:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (SMIN, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfmuladd")]
+)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e7ffeeb9cd64..913a775eec7b 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6395,21 +6395,21 @@
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
+ (match_operand 6 "const_int_operand" " i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (commutative_float_binop_nofrm:VF
- (vec_duplicate:VF
- (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (commutative_float_binop_nofrm:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
index 101ad573aef0..2953d18c6471 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
@@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <)
DEF_MINMAX_VX (min, 256, double, <)
DEF_MINMAX_VX (min, 512, double, <)
-/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times
{vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
index 004a95cd05d6..db156ac23b5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
@@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <=)
DEF_MINMAX_VX (min, 256, double, <=)
DEF_MINMAX_VX (min, 512, double, <=)
-/* { dg-final { scan-assembler-times
{vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times
{vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index bbbbc52a7811..7e56330d9f22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -18,6 +18,8 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -32,3 +34,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index 912c037126d3..e674cf7245a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -18,6 +18,8 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (float, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
+DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
+DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -33,3 +35,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 1664ac7dbce1..b36e966c21c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -14,6 +14,8 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (double, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
+DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
+DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -25,3 +27,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 7d251c032b49..1914b18643c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -17,5 +17,5 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 10aac1f87455..f8dab3749621 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -17,5 +17,5 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index b10261f077d0..909770f70711 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -13,3 +13,4 @@
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 09940e9af4aa..c703ed67860e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -18,6 +18,10 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -33,3 +37,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv,
VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 42adaefe0e7e..99b84dd681ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -18,6 +18,10 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -33,3 +37,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv,
VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 021296984bb8..889fed2c83ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -14,6 +14,10 @@ DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc,
VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -25,3 +29,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv,
VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfmin.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
index b43b7dc5a97d..90436a298c2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
@@ -123,3 +123,84 @@
DEF_VF_BINOP_REVERSE_CASE_1 (T, OP, NAME, BODY)
#endif
+
+#define DEF_MIN_0(T)
\
+ static inline T test_##T##_min_0 (T a, T b) { return a > b ? b : a; }
+
+#define DEF_MIN_1(T)
\
+ static inline T test_##T##_min_1 (T a, T b) { return a >= b ? b : a; }
+
+DEF_MIN_0 (_Float16)
+DEF_MIN_0 (float)
+DEF_MIN_0 (double)
+
+DEF_MIN_1 (_Float16)
+DEF_MIN_1 (float)
+DEF_MIN_1 (double)
+
+#define MIN_FUNC_0(T) test_##T##_min_0
+#define MIN_FUNC_0_WRAP(T) MIN_FUNC_0 (T)
+
+#define MIN_FUNC_1(T) test_##T##_min_1
+#define MIN_FUNC_1_WRAP(T) MIN_FUNC_1 (T)
+
+#define DEF_VF_BINOP_CASE_2(T, FUNC, NAME)
\
+ void test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (T *restrict out,
\
+ T *restrict in, T f, \
+ unsigned n) \
+ {
\
+ for (unsigned i = 0; i < n; i++)
\
+ out[i] = FUNC (in[i], f);
\
+ }
+#define DEF_VF_BINOP_CASE_2_WRAP(T, FUNC, NAME)
\
+ DEF_VF_BINOP_CASE_2 (T, FUNC, NAME)
+#define RUN_VF_BINOP_CASE_2(T, NAME, FUNC, out, in, f, n)
\
+ test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (out, in, f, n)
+#define RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n)
\
+ RUN_VF_BINOP_CASE_2 (T, NAME, FUNC, out, in, f, n)
+
+#define DEF_VF_BINOP_CASE_3(T, FUNC, NAME, BODY)
\
+ void test_vf_binop_##NAME##_##FUNC##_##T##_case_3 (T *restrict out,
\
+ T *restrict in, T f, \
+ unsigned n) \
+ {
\
+ unsigned k = 0;
\
+ T tmp = f + 3;
\
+
\
+ while (k < n)
\
+ {
\
+ tmp = tmp * 0x7.ap3; \
+ BODY (FUNC) \
+ }
\
+ }
+#define DEF_VF_BINOP_CASE_3_WRAP(T, FUNC, NAME, BODY)
\
+ DEF_VF_BINOP_CASE_3 (T, FUNC, NAME, BODY)
+
+#define VF_BINOP_FUNC_BODY(func)
\
+ out[k + 0] = func (in[k + 0], tmp);
\
+ out[k + 1] = func (in[k + 1], tmp);
\
+ k += 2;
+
+#define VF_BINOP_FUNC_BODY_X4(op)
\
+ VF_BINOP_FUNC_BODY (op)
\
+ VF_BINOP_FUNC_BODY (op)
+
+#define VF_BINOP_FUNC_BODY_X8(op)
\
+ VF_BINOP_FUNC_BODY_X4 (op)
\
+ VF_BINOP_FUNC_BODY_X4 (op)
+
+#define VF_BINOP_FUNC_BODY_X16(op)
\
+ VF_BINOP_FUNC_BODY_X8 (op)
\
+ VF_BINOP_FUNC_BODY_X8 (op)
+
+#define VF_BINOP_FUNC_BODY_X32(op)
\
+ VF_BINOP_FUNC_BODY_X16 (op)
\
+ VF_BINOP_FUNC_BODY_X16 (op)
+
+#define VF_BINOP_FUNC_BODY_X64(op)
\
+ VF_BINOP_FUNC_BODY_X32 (op)
\
+ VF_BINOP_FUNC_BODY_X32 (op)
+
+#define VF_BINOP_FUNC_BODY_X128(op)
\
+ VF_BINOP_FUNC_BODY_X64 (op)
\
+ VF_BINOP_FUNC_BODY_X64 (op)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index fb902798bf72..e6ddd1ebb4f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -301,4 +301,151 @@ double TEST_BINOP_DATA(double, rdiv)[][4][N] =
},
};
+_Float16 TEST_BINOP_DATA(_Float16, min)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
0x1.6f80000000000p+4f16,
+ },
+ {
+ 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
0x1.0000000000000p+0f16,
+ 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
0x1.0000000000000p+0f16,
+ 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
0x1.0000000000000p+0f16,
+ 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
0x1.0000000000000p+0f16,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
-0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
-0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
-0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
-0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
0x1.0000000000000p+0f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
-0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
-0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ },
+ {
+ { -0x1.0000000000000p+0f16 },
+ {
+ -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
-0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+ -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
-0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+ 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
0x1.96c0000000000p+4f16,
+ -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
-0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+ },
+ {
+ -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
-0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+ -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
-0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+ -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16,
-0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16,
+ -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
-0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+ },
+ },
+};
+
+float TEST_BINOP_DATA(float, min)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f },
+ {
+ 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
0x1.8fe1540000000p+60f,
+ 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
0x1.b8b5320000000p+62f,
+ 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
0x1.a4eb340000000p+61f,
+ 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
0x1.6faeda0000000p+60f,
+ },
+ {
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
0x1.0000000000000p+0f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
0x1.0000000000000p+0f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
0x1.0000000000000p+0f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
0x1.0000000000000p+0f,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0f },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
-0x1.53e0ba0000000p+61f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
0x1.c3397c0000000p+62f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
-0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
-0x1.94d2a80000000p+62f,
+ },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
-0x1.53e0ba0000000p+61f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
0x1.0000000000000p+0f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
-0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
-0x1.94d2a80000000p+62f,
+ },
+ },
+ {
+ { -0x1.bc16d60000000p+59f },
+ {
+ -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
-0x1.062a340000000p+61f,
+ -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
-0x1.e573960000000p+63f,
+ 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
0x1.96d5c20000000p+60f,
+ -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
-0x1.08eb620000000p+61f,
+ },
+ {
+ -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
-0x1.062a340000000p+61f,
+ -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
-0x1.e573960000000p+63f,
+ -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f,
-0x1.bc16d60000000p+59f,
+ -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
-0x1.08eb620000000p+61f,
+ },
+ },
+};
+
+double TEST_BINOP_DATA(double, min)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0 },
+ {
+ 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
0x1.8fe1565f12a78p+508,
+ 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
0x1.b8b533d821ccap+510,
+ 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
0x1.a4eb35b744a54p+509,
+ 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
0x1.6faedb6395f48p+508,
+ },
+ {
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
0x1.0000000000000p+0,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
0x1.0000000000000p+0,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
0x1.0000000000000p+0,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
0x1.0000000000000p+0,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0 },
+ {
+ -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
-0x1.53e0bc0170fe8p+509,
+ 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
0x1.c3397ceebc142p+510,
+ -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
-0x1.ffe2046f999e3p+511,
+ -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
-0x1.94d2a9003ee18p+510,
+ },
+ {
+ -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
-0x1.53e0bc0170fe8p+509,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
0x1.0000000000000p+0,
+ -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
-0x1.ffe2046f999e3p+511,
+ -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
-0x1.94d2a9003ee18p+510,
+ },
+ },
+ {
+ { -0x1.317e5ef3ab327p+508 },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
-0x1.062a35a13cec0p+509,
+ -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
-0x1.e5739808c344dp+511,
+ 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
0x1.96d5c3ca79e38p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
-0x1.08eb6307cef78p+509,
+ },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
-0x1.062a35a13cec0p+509,
+ -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
-0x1.e5739808c344dp+511,
+ -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508,
-0x1.317e5ef3ab327p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
-0x1.08eb6307cef78p+509,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
new file mode 100644
index 000000000000..c84c77348eae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T _Float16
+#define FUNC MIN_FUNC_0_WRAP(T)
+#define NAME min
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME,
FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
new file mode 100644
index 000000000000..a2d024e24f73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define FUNC MIN_FUNC_0_WRAP(T)
+#define NAME min
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME,
FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
new file mode 100644
index 000000000000..9a66f18bc83f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T double
+#define FUNC MIN_FUNC_0_WRAP(T)
+#define NAME min
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME,
FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
