https://gcc.gnu.org/g:07ad8f1298aa1983aec8cd87e1b8d877c44e3c03
commit r16-3109-g07ad8f1298aa1983aec8cd87e1b8d877c44e3c03
Author: H.J. Lu <hjl.to...@gmail.com>
Date: Sat Aug 9 14:44:36 2025 -0700
asm-hard-reg-1.c: Adjust scan for x86 with ia32, x32 and lp64
Since i?86 and x86_64 GCC can generate codes for ia32, x32 and lp64, adjust
asm-hard-reg-1.c scan for x86 with ia32, x32 and lp64.
PR testsuite/121205
* gcc.dg/asm-hard-reg-1.c: Adjust scan for x86 with ia32, x32 and
lp64.
Signed-off-by: H.J. Lu <hjl.to...@gmail.com>
Diff:
---
gcc/testsuite/gcc.dg/asm-hard-reg-1.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-1.c
b/gcc/testsuite/gcc.dg/asm-hard-reg-1.c
index 6a5a9ada45f0..8cefb6e6980c 100644
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-1.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-1.c
@@ -22,10 +22,11 @@
/* { dg-final { scan-assembler-times "foo\t%r4" 8 { target { s390*-*-* } } } }
*/
#elif defined (__x86_64__)
# define GPR "{rcx}"
-/* { dg-final { scan-assembler-times "foo\t%cl" 2 { target { x86_64-*-* } } }
} */
-/* { dg-final { scan-assembler-times "foo\t%cx" 2 { target { x86_64-*-* } } }
} */
-/* { dg-final { scan-assembler-times "foo\t%ecx" 2 { target { x86_64-*-* } } }
} */
-/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { x86_64-*-* } } }
} */
+/* { dg-final { scan-assembler-times "foo\t%cl" 2 { target { i?86-*-*
x86_64-*-* } } } } */
+/* { dg-final { scan-assembler-times "foo\t%cx" 2 { target { i?86-*-*
x86_64-*-* } } } } */
+/* { dg-final { scan-assembler-times "foo\t%ecx" 2 { target { { i?86-*-*
x86_64-*-* } && lp64 } } } } */
+/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { { i?86-*-*
x86_64-*-* } && lp64 } } } } */
+/* { dg-final { scan-assembler-times "foo\t%ecx" 4 { target { { i?86-*-*
x86_64-*-* } && { ! lp64 } } } } } */
#endif
char
