The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
763de945f6b4... Change bellow in comments to below
It previously pointed to:
6ae24e5065ec... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------
6ae24e5... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
9f3ebf2... RISC-V: Add testcase for rv32 SAT_MUL from uint64
8a0241b... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
64c0c04... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
ee2202e... RISC-V: Make zero-stride load broadcast a tunable.
907baff... [RISC-V] Detect new fusions for RISC-V
e24b66b... RISCV: Remove the v extension requirement for sat scalar ru
aeae7c6... RISC-V: Add test for vec_duplicate + vssub.vv combine case
4ee8f05... RISC-V: Add test for vec_duplicate + vssub.vv combine case
374083a... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
7735ae7... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
decbd28... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
16b14d2... [RISC-V][PR target/120642] Avoid propagating constant AVL f
f8a92eb... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
e88c415... RISC-V: Do not use vsetivli for THeadVector.
fbe8a3f... RISC-V: Ignore non-types in builtin function hash.
07f75a5... [PATCH] riscv: allow zero in zacas subword atomic cas
045d0c6... [committed][RISC-V] Fix testsuite fallout from check-functi
85ae875... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
03d7be4... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
46f3e46... RISC-V: prefetch: fix LRA failing to allocate reg [PR118241
ae406c5... RISC-V: prefetch: const offset needs to have 5 bits zero, n
2c8e307... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
60e1928... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
b3df1cb... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
d7f7353... [RISC-V] Add basic instrumentation to fusion detection
ede8592... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
7363e56... Refactor record_function_versions.
477d40b... [RISC-V][PR target/118886] Refine when two insns are signal
7c41709... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
09f1fdd... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
102e915... [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTE
76d99d9... [RISC-V] Correct CFA notes for stack-clash protection [PR12
c20878b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
de5e9aa... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
927d0cb... RISC-V: Reconcile the existing test due to cost model chang
f6f8088... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
4c823d9... RISC-V: Ignore -Oz for most rvv testcase [NFC]
13b49dd... RISC-V: Primary vector pipeline model for sifive 7 series
71cc3ca... RISC-V: Adding B ext, fp16 and missing scalar instruction t
0be8dc1... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
6ce0821... RISC-V: Refactor the function bitmap_union_of_preds_with_en
101b601... RISC-V: Add pipeline-checker script
822bd8f... [sanitizer_common] Fix build on ppc64+musl (#120036)
5ad1aa3... [RISC-V][PR target/119971] Avoid losing shift count masking
058acd7... RISC-V: update prepare_ternary_operands to handle vector-sc
14c1c41... RISC-V: Fix build issue
329a20b... RISC-V: Add comment and reorder the the include files in ri
30bc81d... RISC-V: Add Profiles RVA/B23S64 support.
7579e0c... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
a0cca39... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
0378e1e... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
26cde1e... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
28a7e66... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
5ccee56... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host
30e7306... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
6c397a7... RISC-V: Fix ICE for expand_select_vldi [PR120652]
4431d24... [RISC-V] Force several tests to use rocket tuning
2ea35c1... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
7ec4372... RISC-V: Add test for vec_duplicate + vminu.vv combine case
1b7fcb4... RISC-V: Add test for vec_duplicate + vminu.vv combine case
34c5807... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
d2b21c2... RISC-V: Add generic tune as default.
3becefc... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f4beb34... RISC-V: Adding cost model for zilsd
16a379b... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
7ad53e8... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
b7ccbdc... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
a97eb08... [PATCH v1] RISC-V: Use scratch reg for loop control
9fe9f65... RISC-V: Add -fno-pie flags to testcases
5abb21b... RISC-V: Refine VX combine test case 0 to avoid code duplica
9f15440... RISC-V: Update Profiles string in RV23.
05bc63f... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
a0d1d0c... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
4af1a95... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
31baabf... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
0363f53... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
b0d572c... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
308422b... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
c545dd7... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
48eaa96... RISC-V: Prevent speculative vsetvl insn scheduling
ec9f7a5... RISC-V: Add patterns for vector-scalar negate-(multiply-add
7469cb5... RISC-V: testsuite: fix an obvious build error
01bbac9... RISC-V: Regen riscv-ext.texi [NFC]
e72e3b9... RISC-V: Add test for vec_duplicate + vremu.vv combine case
1b74e83... RISC-V: Add test for vec_duplicate + vremu.vv combine case
0cb8e0f... RISC-V: Reconcile the existing test for vremu.vx combine
3a987c7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
dc318d1... [RISC-V] Enable more if-conversion on RISC-V
c3c93b3... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
19ad8d1... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
d981ce1... RISC-V: Reconcile the existing test for vrem.vx combine
0a7f235... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
3770993... RISC-V: frm/mode-switch: robustify call_insn backtracking [
64b1aa9... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
2d2ea24... RISC-V: frm/mode-switch: remove dubious frm edge insertion
41313ac... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
96541e6... [RISC-V] Handle 32bit operands in condition for conditional
2283c7e... [to-be-committed][RISC-V] Handle 32bit operands in conditio
71cc200... RISC-V: Reconcile the existing test for vdivu.vx combine
275b04c... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
cffd80f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
bcdf931... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
27bee9e... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
7e1fbe7... [RISC-V] Improve signed division by 2^n
8af974e... RISC-V: Don't use structured binding in riscv-common.cc
7c46682... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
957f90a... [RISC-V] Improve sequences to generate -1, 1 in some cases.
a8537f7... RISC-V: Support Ssu64xl extension.
8b3cd36... RISC-V: Support Sstvecd extension.
596f77f... RISC-V: Support Sstvala extension.
ef7643f... RISC-V: Support Sscounterenw extension.
bb1262a... RISC-V: Support Ssccptr extension.
a6a08cd... RISC-V: Support Smrnmi extension.
883e1d8... RISC-V: Support Sm/scsrind extensions.
3454cda... RISC-V: Update extension defination.
ac488b6... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
05a5edf... [PATCH v2] RISC-V: Add svbare extension.
521f66a... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
2626c79... RISC-V: Add Shlcofideleg extension.
e77de75... RISC-V: Reconcile the existing test for vdiv.vx combine
0eed140... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
d712389... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
c89fb82... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
3341d68... RISC-V: Use helper function to get FPR to VR move cost
8db0209... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
b909545... [PATCH] RISC-V: Add smcntrpmf extension.
4f4e95f... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
4fc2870... RISC-V: Implement full-featured iterator for riscv_subset_l
f483250... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
4e64eea... RISC-V: Fix line too long format issue for autovect.md [NFC
854c64a... RISC-V: Add test cases for avg_ceil vaadd implementation
a056201... RISC-V: Reconcile the existing test for avg_ceil
c58ba0a... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
672d63a... RISC-V: Add minimal support of double trap extension 1.0
37a01a9... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
67f43b2... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
3e7b7fe... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
c0bd9e5... RISC-V: Avoid division by zero in check_builtin_call [PR120
e42582f... RISC-V: Add test cases for avg_floor vaadd implementation
2af6dd9... RISC-V: Reconcile the existing test for avg_floor
b02fdf3... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
2cfc802... [RISC-V] Add andi+bclr synthesis
014f336... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
88dd4a6... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
4a8ee4e... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
0eb7c72... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5f22320... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
d9ce8e5... [RISC-V] shift+and+shift for logical and synthesis
5eff5f4... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
4f9c151... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
a76c032... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
dc2342a... RISC-V: Support CPUs in -march.
d8e1279... RISC-V: Add autovec mode param.
02758bf... RISC-V: Default-initialize variable.
48e4aed... RISC-V: Fix some dynamic LMUL costing.
8c5d12e... [RISC-V] Clear both upper and lower bits using 3 shifts
79854f9... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
4ead2b0... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
cba7674... [RISC-V] Clear high or low bits using shift pairs
fa0d12f... [RISC-V] Improve (x << C1) + C2 split code
ca792e2... [RISC-V][PR target/120368] Fix 32bit shift on rv64
54f065e... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
ac3460d... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
8e8facb... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
d93e4e5... [RISC-V] Infrastructure of synthesizing logical AND with co
ba16939... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
4c6285f... [PATCH v2 1/2] The following changes enable P8700 processor
eda6b3e... [RISC-V] Avoid multiple assignments to output object
dc4f8e8... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
b13bb6a... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
81734e7... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
323993b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
c38b9b8... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
469cc6c... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
cec32c2... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f6327e6... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
ab141c0... [committed][RISC-V][PR target/120333] Remove bogus bext pat
ca3b668... [RISC-V] Fix false positive from Wuninitialized
55085ab... RISC-V: Fix the warning of temporary object dangling refere
fc618ec... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
77ea0ac... RISC-V: Support Zilsd code gen
c36c104... RISC-V: Add new operand constraint: cR
de9601a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
c14b79c... [RISC-V] Avoid setting output object more than once in IOR/
5d221ae... RISC-V: Since the loop increment i++ is unreachable, the lo
cca0dce... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
46c3d92... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
a538b05... Make end_sequence return the insn sequence
51d3403... RISC-V: Reuse test name for vx combine test data [NFC]
c10fe8f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
2f312a4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
52a93e4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
3b38a3f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b02e980... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b51a35c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b79bf32... RISC-V: Adjust vx combine test case to avoid name conflict
0ae5ea9... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
1c91ecf... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
19dbfce... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
f74b7cc... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
4ad5162... RISC-V: Add augmented hypervisor series extensions.
1d459f6... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
89e5968... RISC-V: Regen riscv-ext.opt.urls
98d34e3... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
7d20250... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
1151782... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
13c9dc3... RISC-V: Introduce riscv_ext_info_t to hold extension metada
e4af132... RISC-V: Adjust riscv_can_inline_p
0c85dfe... RISC-V: Generate extension table in documentation from risc
ec13b92... RISC-V: Use riscv-ext.def to generate target options and va
991a5b5... RISC-V: Introduce riscv-ext*.def to define extensions
f841fc0... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
2d190e7... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
197e4a8... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
423a6fc... RISC-V: Support for zilsd and zclsd extensions.
091b0a7... testsuite: Fix RISC-V arch-52.c format issue.
f299534... RISC-V: Support RISC-V Profiles 23.
762080c... RISC-V: Support RISC-V Profiles 20/22.
4679326... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
665c8e3... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
c58e7cb... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
f1ddbef... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
07d884d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
c9a4e7b... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
a0cef8c... RISC-V: Separate the test running of rvv vx_vf
f8d665b... [RISC-V][PR target/120137][PR target/120154] Don't create o
9bdbf2c... [PATCH] RISC-V: Minimal support for zama16b extension.
6519c42... [RISC-V] Avoid unnecessary andi with -1 argument
a85d3aa... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
d053780... [PATCH] RISC-V: Recognized svadu and svade extension
c25cb94... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
fae6884... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
77b4d0b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
67fc086... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
074b97c... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
cf9debc... RISC-V: Add gr2vr cost helper function
3dbde19... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
ed28056... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
14ee335... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4bd0c4d... [V2][RISC-V] Trivial permutation constant derivation
739b45a... [RISC-V] Adjust rvv tests after recent jump threading chang
230e928... [PATCH] RISC-V: Implment H modifier for printing the next r
6021cda... [to-be-committed][RISC-V] Adjust testcases and finish regis
832289e... RISC-V: Remove unnecessary frm restore volatile define_insn
26a7c6c... RISC-V: Allow different dynamic floating point mode to be m
67fb8a5... RISC-V: Fix missing implied Zicsr from Zve32x
bfd52bc... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
ddbb041... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
9fdcd6b... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
d79f2cf... RISC-V: Extract vector stepped for expand_const_vector [NFC
c5efbcc... RISC-V: Extract vector duplicate for expand_const_vector [N
1b34877... RISC-V: Extract vec_series for expand_const_vector [NFC]
2cc19b6... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
e7eebae... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
d05ffa6... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
b5f4ff6... [riscv] vec_dup immediate constants in pred_broadcast expan
99f2e82... [RISC-V][PR target/119865] Don't free ggc allocated memory
327b6ed... [RISC-V][PR target/118410] Improve code generation for some
693cba2... [RISC-V] Fix missed bext discovery
48208b7... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
1cbc416... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
b8ae77a... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
763de94... Change bellow in comments to below
0bdb4d4... [RISC-V] Restrict generic-vector-ooo DFA
bf08d63... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
08c2796... [RISC-V] Fix wrong CFA during stack probe
69057e8... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
5b8472a... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
324e9a9... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
26e7498... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
93c2fcd... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
833cce5... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
c4c34c8... RISC-V: Refine the test case for vector avg_floor and avg_c
3a87484... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
e077fe0... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
4ea7601... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
8b53c83... RISC-V: Support RVVDImode for avg3_ceil auto vect
820f9d5... RISC-V: Fix vsetvl merge rule.
b8bea84... RISC-V: Refine the scalar SAT_* test cases
42743b8... RISC-V: Support RVVDImode for avg3_floor auto vect
83974e4... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
facb0b8... RISC-V: Add testcase for rv32 SAT_MUL from uint64
e0bc128... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
866b659... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
8d827db... RISC-V: Make zero-stride load broadcast a tunable.
635ac77... [RISC-V] Detect new fusions for RISC-V
20fcd8a... RISCV: Remove the v extension requirement for sat scalar ru
3ca3c6d... RISC-V: Add test for vec_duplicate + vssub.vv combine case
0934c87... RISC-V: Add test for vec_duplicate + vssub.vv combine case
a4c8e28... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
c5a3303... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
5d6fd53... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
b8558ce... [RISC-V][PR target/120642] Avoid propagating constant AVL f
e1b3e2b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
d985f7a... RISC-V: Do not use vsetivli for THeadVector.
94db940... RISC-V: Ignore non-types in builtin function hash.
eddfc55... [committed][RISC-V] Fix testsuite fallout from check-functi
57b108b... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
04628a1... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
2ba4718... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
a82205f... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
9521224... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
342e0f6... [RISC-V] Add basic instrumentation to fusion detection
ed2c972... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
0190716... Refactor record_function_versions.
b8613cb... [RISC-V][PR target/118886] Refine when two insns are signal
ee451a0... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
17f6b67... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
7a4c77b... [RISC-V] Correct CFA notes for stack-clash protection [PR12
631cf6b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
5086e8b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
e33555b... RISC-V: Reconcile the existing test due to cost model chang
2e78bb2... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
d1ec2e5... RISC-V: Ignore -Oz for most rvv testcase [NFC]
6b0f5fe... RISC-V: Primary vector pipeline model for sifive 7 series
d9f0595... RISC-V: Adding B ext, fp16 and missing scalar instruction t
2b19c58... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
85765e5... RISC-V: Refactor the function bitmap_union_of_preds_with_en
fba8b6e... RISC-V: Add pipeline-checker script
00fac0b... [sanitizer_common] Fix build on ppc64+musl (#120036)
310914d... [RISC-V][PR target/119971] Avoid losing shift count masking
468cffa... RISC-V: update prepare_ternary_operands to handle vector-sc
7bef4a4... RISC-V: Fix build issue
21a280f... RISC-V: Add comment and reorder the the include files in ri
ed0e22e... RISC-V: Add Profiles RVA/B23S64 support.
38505ba... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
6521311... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
786c243... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
e3cb2ec... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
7d12abe... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host
cef5e1c... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
dcdaa59... RISC-V: Fix ICE for expand_select_vldi [PR120652]
ba2759d... [RISC-V] Force several tests to use rocket tuning
2abb0cc... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
dced81d... RISC-V: Add test for vec_duplicate + vminu.vv combine case
6374a66... RISC-V: Add test for vec_duplicate + vminu.vv combine case
0e4f34c... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
5fb7812... RISC-V: Add generic tune as default.
266be98... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
786c105... RISC-V: Adding cost model for zilsd
a82b84b... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
70cb9df... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
df78e45... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
4dd8fe7... [PATCH v1] RISC-V: Use scratch reg for loop control
7fd0df1... RISC-V: Add -fno-pie flags to testcases
6c5006c... RISC-V: Refine VX combine test case 0 to avoid code duplica
8490803... RISC-V: Update Profiles string in RV23.
7ed9776... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
6a37b4b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
73635d8... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
8c01d04... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
0960d4b... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
64fc9a9... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
9ae4084... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
97a13af... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
7cea665... RISC-V: Prevent speculative vsetvl insn scheduling
0f9e3fb... RISC-V: Add patterns for vector-scalar negate-(multiply-add
055b964... RISC-V: testsuite: fix an obvious build error
318ee82... RISC-V: Regen riscv-ext.texi [NFC]
e54ba9f... RISC-V: Add test for vec_duplicate + vremu.vv combine case
352cd26... RISC-V: Add test for vec_duplicate + vremu.vv combine case
c948a9f... RISC-V: Reconcile the existing test for vremu.vx combine
a905f01... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
42038b7... [RISC-V] Enable more if-conversion on RISC-V
2ed33da... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
115afc1... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
579ff53... RISC-V: Reconcile the existing test for vrem.vx combine
937fc54... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
5820ee6... RISC-V: frm/mode-switch: robustify call_insn backtracking [
d3e584d... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
82333ed... RISC-V: frm/mode-switch: remove dubious frm edge insertion
9f72bfe... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
b6a2b75... [RISC-V] Handle 32bit operands in condition for conditional
f86dd7d... [to-be-committed][RISC-V] Handle 32bit operands in conditio
9c4f680... RISC-V: Reconcile the existing test for vdivu.vx combine
48668f8... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
2a2b2fa... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
d1d5fdf... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
3daa678... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
680eb45... [RISC-V] Improve signed division by 2^n
772f741... RISC-V: Don't use structured binding in riscv-common.cc
358e3e7... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
38649b2... [RISC-V] Improve sequences to generate -1, 1 in some cases.
d0b4acf... RISC-V: Support Ssu64xl extension.
9a07898... RISC-V: Support Sstvecd extension.
48a5024... RISC-V: Support Sstvala extension.
dd2ede7... RISC-V: Support Sscounterenw extension.
ccdbacd... RISC-V: Support Ssccptr extension.
0900666... RISC-V: Support Smrnmi extension.
fcf5184... RISC-V: Support Sm/scsrind extensions.
7be775b... RISC-V: Update extension defination.
259286d... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
2b27d40... [PATCH v2] RISC-V: Add svbare extension.
7f77969... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
2fbcc82... RISC-V: Add Shlcofideleg extension.
da9ec3b... RISC-V: Reconcile the existing test for vdiv.vx combine
e69c82d... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
d6292a3... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
c46ca69... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
5683360... RISC-V: Use helper function to get FPR to VR move cost
19dbe09... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
f1d4078... [PATCH] RISC-V: Add smcntrpmf extension.
e785b6c... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
55eb9e7... RISC-V: Implement full-featured iterator for riscv_subset_l
d4558db... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
f974122... RISC-V: Fix line too long format issue for autovect.md [NFC
1ee144c... RISC-V: Add test cases for avg_ceil vaadd implementation
f2fac47... RISC-V: Reconcile the existing test for avg_ceil
4b90529... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
bcc01ae... RISC-V: Add minimal support of double trap extension 1.0
925b08e... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
602c779... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
325bc4d... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
471c5ca... RISC-V: Avoid division by zero in check_builtin_call [PR120
28f5689... RISC-V: Add test cases for avg_floor vaadd implementation
531ba01... RISC-V: Reconcile the existing test for avg_floor
db8d20c... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
b81f4e6... [RISC-V] Add andi+bclr synthesis
7e355a1... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
379a1e8... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
1176178... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
443544e... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5d4ed37... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
7b9c940... [RISC-V] shift+and+shift for logical and synthesis
2cb7dfe... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
9bb6cb1... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
c3ccaeb... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
d623e56... RISC-V: Support CPUs in -march.
d945530... RISC-V: Add autovec mode param.
d70217b... RISC-V: Default-initialize variable.
07c935e... RISC-V: Fix some dynamic LMUL costing.
86e3149... [RISC-V] Clear both upper and lower bits using 3 shifts
e9fcf56... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
ff8ae1f... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
e168199... [RISC-V] Clear high or low bits using shift pairs
1800970... [RISC-V] Improve (x << C1) + C2 split code
22afab2... [RISC-V][PR target/120368] Fix 32bit shift on rv64
a031409... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
b29ef1d... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
bbf2554... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
db7b07b... [RISC-V] Infrastructure of synthesizing logical AND with co
7fc9ea3... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
a299c80... [PATCH v2 1/2] The following changes enable P8700 processor
9a12ab9... [RISC-V] Avoid multiple assignments to output object
3f02e70... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
63d4c14... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
79af32b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a61bdc6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
eab2ec4... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
9fa6927... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0c11523... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
fc82eb2... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
99ec4f5... [committed][RISC-V][PR target/120333] Remove bogus bext pat
091ab94... [RISC-V] Fix false positive from Wuninitialized
1e14441... RISC-V: Fix the warning of temporary object dangling refere
6f72204... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
461df40... RISC-V: Support Zilsd code gen
cd7a452... RISC-V: Add new operand constraint: cR
b65055e... [RISC-V] Fix ICE due to bogus use of gen_rtvec
e8fa4f5... [RISC-V] Avoid setting output object more than once in IOR/
451b730... RISC-V: Since the loop increment i++ is unreachable, the lo
8bf87f6... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
3895fb9... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
29efbaf... Make end_sequence return the insn sequence
db7d25f... RISC-V: Reuse test name for vx combine test data [NFC]
c0013e0... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
e0f154c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
1f05f3d... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
ede937e... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
aaf3bbc... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
af21cd7... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b96371d... RISC-V: Adjust vx combine test case to avoid name conflict
c382fb4... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
bf8f136... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
d9249d2... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
2e8b43b... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
c76dafe... RISC-V: Add augmented hypervisor series extensions.
79a7b67... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
50aaf5d... RISC-V: Regen riscv-ext.opt.urls
3bc9532... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
ff81339... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
de2de27... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
eac0419... RISC-V: Introduce riscv_ext_info_t to hold extension metada
fcadee7... RISC-V: Adjust riscv_can_inline_p
5a3297a... RISC-V: Generate extension table in documentation from risc
426bc13... RISC-V: Use riscv-ext.def to generate target options and va
33320cb... RISC-V: Introduce riscv-ext*.def to define extensions
dc93659... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
6fa627e... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
0a3c888... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
5104390... RISC-V: Support for zilsd and zclsd extensions.
bb3f52e... testsuite: Fix RISC-V arch-52.c format issue.
f08ba94... RISC-V: Support RISC-V Profiles 23.
f2e5a82... RISC-V: Support RISC-V Profiles 20/22.
cd47f8d... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
85998f2... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
9fb73d6... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
d334d95... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
1c01c23... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
32ad857... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
6cb8d32... RISC-V: Separate the test running of rvv vx_vf
83782c5... [RISC-V][PR target/120137][PR target/120154] Don't create o
0062d6a... [PATCH] RISC-V: Minimal support for zama16b extension.
5408f5d... [RISC-V] Avoid unnecessary andi with -1 argument
91c7828... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
39c180d... [PATCH] RISC-V: Recognized svadu and svade extension
7508d78... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
8f30e58... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
8cfb089... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
3a7248f... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
3d37606... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
6d876dd... RISC-V: Add gr2vr cost helper function
467cd89... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
e899499... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
2bd9a08... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
70a3a1e... [V2][RISC-V] Trivial permutation constant derivation
03cdf8a... [RISC-V] Adjust rvv tests after recent jump threading chang
9090b44... [PATCH] RISC-V: Implment H modifier for printing the next r
3051776... [to-be-committed][RISC-V] Adjust testcases and finish regis
c4243db... RISC-V: Remove unnecessary frm restore volatile define_insn
94418d3... RISC-V: Allow different dynamic floating point mode to be m
8e26f37... RISC-V: Fix missing implied Zicsr from Zve32x
eea8d50... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
2f3f601... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
6675719... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
4077ce6... RISC-V: Extract vector stepped for expand_const_vector [NFC
c7b18d2... RISC-V: Extract vector duplicate for expand_const_vector [N
7bc3d61... RISC-V: Extract vec_series for expand_const_vector [NFC]
de604dd... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
12dcf63... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
d3c54b6... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
d3bc131... [riscv] vec_dup immediate constants in pred_broadcast expan
2b051e8... [RISC-V][PR target/119865] Don't free ggc allocated memory
8f90305... [RISC-V][PR target/118410] Improve code generation for some
3dec414... [RISC-V] Fix missed bext discovery
519ab56... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
ac7a631... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
132f778... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
420b163... tree-sra: Fix grp_covered flag computation when totally sca (*)
156c3ee... testsuite: Fix overflow in gcc.dg/vect/pr116125.c (*)
2f39b1b... Daily bump. (*)
381d014... ada: Fix generation of Initialize and Adjust calls (*)
0bccb1e... ada: Remove obsolete code from Safe_Unchecked_Type_Conversi (*)
2b05983... ada: Fix assertion failure on aggregate with controlled com (*)
c6b571c... ada: Tune recent change for bit-packed arrays to help GNATp (*)
633f73c... ada: Fix wrong indirect access to bit-packed array in itera (*)
e28f90f... ada: exp_util.adb: prevent infinite loop in case of broken (*)
9023bcd... OpenMP: Fix implicit 'declare target' for <ostream> (*)
dd10f19... Avoid SIGSEGV in nvptx 'mkoffload' for voluminous PTX code (*)
5a3428f... Add 'libgomp.c++/target-valarray-1.C' (*)
299a7f5... libgomp: Add testcases for concurrent access to standard C+ (*)
a7c5f7a... libgomp: Add testcases for concurrent access to standard C+ (*)
6e40fb2... libgomp: Add testcases for the standard C++ math library on (*)
259451b... Add 'libgomp.c++/target-flex-[...].C' test cases (*)
e4dbeb0... Defuse 'RESULT_DECL' check in 'pass_nrv' (for offloading co (*)
7a9b7f8... 'TYPE_EMPTY_P' vs. code offloading [PR120308] (*)
a5df3ae... Add 'libgomp.c-c++-common/target-abi-struct-1-O0.c', 'libgo (*)
0a708f6... libgomp.c/target-map-zero-sized-3.c: Fix code for non-USM o (*)
66aa8ad... GCN, nvptx offloading: Restrain 'WARNING: program timed out (*)
f9d558a... GCN, nvptx offloading: Restrain 'WARNING: program timed out (*)
caca3a9... nvptx: Support '-march=sm_61' (*)
2b105cb... nvptx: Support '-mptx=5.0' (*)
eca0a53... Adjust 'libgomp.c++/target-cdtor-{1,2}.C' for 'targetm.cxx. (*)
ebc72ad... GCN, nvptx offloading: Host/device compatibility: Itanium C (*)
3d44997... Add 'libgomp.c-c++-common/target-cdtor-1.c' (*)
655f833... GCN: Properly switch sections in 'gcn_hsa_declare_function_ (*)
e4677f3... Adjust 'libgomp.c++/target-exceptions-pr118794-1.C' for 'ta (*)
ff9bd93... Daily bump. (*)
d80498a... Ada: Fix wrong tag in style check warnings (*)
b8be49c... aarch64: Tweak handling of general SVE permutes [PR121027] (*)
a413f83... aarch64: Fix LD1Q and ST1Q failures for big-endian (*)
79a9996... testsuite: Add -funwind-tables to sve*/pfalse* tests (*)
24a6fe0... aarch64: Extend HVLA permutations to big-endian (*)
526efb6... aarch64: Fix endianness of DFmode vector constants (*)
c237162... aarch64: Some fixes for SVE INDEX constants (*)
abacc79... Make the RTL frontend set REG_NREGS correctly (*)
0b6038c... ext-dce: Fix subreg_lsb is_constant assumption (2) (*)
d88c1b7... aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR11 (*)
eca9778... aarch64: Fix neon-sve-bridge.c failures for big-endian (*)
9e8af68... ext-dce: Fix subreg_lsb is_constant assumption (*)
2363ea8... vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118 (*)
032aca3... Daily bump. (*)
d553ca7... Fortran: fix bogus runtime error with optional procedure ar (*)
16230fa... Daily bump. (*)
f000ed0... libstdc++: Update some baseline_symbols.txt (x32) (*)
69e46e6... Daily bump. (*)
1956645... [PATCH] PR modula2/121164 Modula 2 build failure (*)
ec238c4... rust: Silence a clang warning in borrow-checker-diagnostics (*)
c42eb01... gccrs: Fix narrowing conversion warnings (*)
db11086... Disable parallel testing for 'rust/compile/nr2/compile.exp' (*)
f5afbab... Fix time zone for 'cobol.dg/group2/FUNCTION_DATE___TIME_OMN (*)
2441a52... mmix: Define MAX_FIXED_MODE_SIZE (*)
e1828db... tree-optimization/120924 - up --param uninit-max-chain-len (*)
a8512a6... [PATCH] PR modula2/120912: Request for a procedure to obtai (*)
b37d0b2... tree-optimization/121059 - fixup loop mask query (*)
185a8ba... tree-optimization/121049 - avoid loop masking with even/odd (*)
aa28a33... tree-optimization/121035 - handle stray VN values without e (*)
f0a86bb... [PATCH] [PR modula2/117203] Followup add Delete procedure f (*)
5a5e725... gimple-fold: Fix up big endian _BitInt adjustment [PR121131 (*)
a9a6f24... [PATCH] [PR modula2/120731] error in Strings.Pos causing si (*)
4296f91... [PATCH] [modula2] Comment tidyup in gm2-compiler/M2GCCDecla (*)
ba085e5... [PATCH] PR modula2/120673: Mutually dependent types crash t (*)
d6b1805... Daily bump. (*)
f0401f9... [PATCH] PR modula2/119650: Regenerate target independent do (*)
48e0ad7... [PATCH] PR modula2/120606: FOR loop ICE if the last express (*)
7e4c25e... [PATCH] [PR modula2/119650, PR modula2/117203]: WriteString (*)
10846d8... c++: constexpr array testcase [PR87097] (*)
dee5246... [PATCH] PR modula2/120542: Return statement in the main pro (*)
46e41cf... [PATCH] PR modula2/120474: InOut buffering should flush the (*)
95543c5... LoongArch: Prevent subreg of subreg in CRC [PR 120807] (*)
4249b21... Daily bump. (*)
b355c29... [PATCH] PR modula2/120497: error is generated for good code (*)
1e9255f... [PATCH] PR modula2/120389 Assigning wrong type to an array (*)
ead967d... Fortran: Fix ICE in ASSOCIATE with user defined operator [P (*)
426e9cf... i386: Decouple AMX-AVX512 from AVX10.2 and imply AVX512F (*)
3de4de2... Daily bump. (*)
7dcb644... [PATCH] PR modula2/120389 ICE if assigning a constant char (*)
c9965c3... openmp, fortran: Fix ICE when the procedure name cannot be (*)
1cb95b3... Fortran: Ensure finalizers are created correctly [PR120637] (*)
e54a0c5... crc: Error out on non-constant poly arguments for the crc b (*)
4b4b2c7... Daily bump. (*)
944ecdf... aarch64: PR target/120999: Adjust operands for movprfx alte (*)
6d9253b... aarch64: Fix up commutative and early-clobber markers on co (*)
0588de0... [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTE (*)
bf6b074... RISC-V: prefetch: fix LRA failing to allocate reg [PR118241 (*)
b5d0cfa... RISC-V: prefetch: const offset needs to have 5 bits zero, n (*)
e7d4593... [RISC-V][PR target/118241] Fix data prefetch predicate/cons (*)
4157d43... [RISC-V][PR target/118241] Fix data prefetch predicate/cons (*)
762ca0b... Ada: Add missing guard before accessing the Underlying_Reco (*)
fcc6ce1... x86-64: Add RDI clobber to 64-bit dynamic TLS patterns (*)
3f6e48c... x86-64: Add RDI clobber to tls_global_dynamic_64 patterns (*)
e949298... i386: Remove KEYLOCKER related feature since Panther Lake a (*)
e3f8aa2... Daily bump. (*)
d8f2b4f... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped (*)
8f93b00... [PATCH] riscv: allow zero in zacas subword atomic cas (*)
9ac0baf... Daily bump. (*)
c0900e6... Daily bump. (*)
e6bb28e... PR modula2/120253: Error message column numbers should star (*)
bd817e6... testsuite: Add testcase for already fixed PR [PR120954] (*)
c0dd240... ipa: Disallow signature changes in fun->has_musttail functi (*)
bd6cc4f... c++: Fix up final handling in C++98 [PR120628] (*)
b102e3d... c++: Don't incorrectly reject override after class head nam (*)
f9516f1... c-family: Tweak ptr +- (expr +- cst) FE optimization [PR120 (*)
fcbedca... libstdc++: Fix __uninitialized_default for constexpr case [ (*)
ab37816... libstdc++: Do not use list-initialization in std::span memb (*)
2de64a6... libstdc++: Ensure pool resources meet alignment requirement (*)
6f06b52... Daily bump. (*)
57eae2c... Fix 'main' function in 'gcc.dg/builtin-dynamic-object-size- (*)
63c4d4f... tree-optimization/120780: Support object size for containin (*)
aad3749... aarch64: Add support for NVIDIA GB10 (*)
ba70879... Daily bump. (*)
120efb3... Fortran: Remove corank conformability checks [PR120843] (*)
0f1e4dd... tree-optimization/120358 - bogus PTA with structure access (*)
c625bc9... tree-optimization/118669 - fixup wrongly aligned loads/stor (*)
77066fe... testsuite: add sve hw check to testcase [PR120817] (*)
0ebeed5... tree-optimization/120817 - bogus DSE of .MASK_STORE (*)
b859969... tree-optimization/120927 - 510.parest_r segfault with maske (*)
2c23368... tree-optimization/120944 - bogus VN with volatile copies (*)
cae319d... Daily bump. (*)
dff4652... libstdc++: Fix typo in __size_to_integer(__GLIBCXX_TYPE_INT (*)
7e3c677... nr2.0: late: Correctly initialize funny_error member (*)
6745273... Fortran: Ensure arguments in coarray call get unique compon (*)
887ddb4... Fortran: Fix non-conformable corank on this_image ref [PR12 (*)
4228ec7... Daily bump. (*)
f8f6879... Daily bump. (*)
17f282c... AVR: Fix a typo in avr-mcus.def. (*)
7d27ffd... AVR: Add support for AVR32DAxxS, AVR64DAxxS, AVR128DAxxS de (*)
980a8fe... Daily bump. (*)
(*) This commit already exists in another branch.
Because the reference `refs/vendors/riscv/heads/gcc-15-with-riscv-opts'
matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
