https://gcc.gnu.org/g:1e77645795fdf25ffdb5e9931fd9c946f2261fe2
commit r16-2365-g1e77645795fdf25ffdb5e9931fd9c946f2261fe2 Author: Pan Li <pan2...@intel.com> Date: Sat Jul 19 10:49:15 2025 +0800 RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] The previous test case doesn't leverage the right test helper macro, it should be DEF_AVG_0_WRAP instead of DEF_AVG_0. We prefer the test function name is test_avg_floor_int64_t_int32_t_0 instead of test_avg_floor_WT_NT_0 for DEF_AVG_0(WT, NT). The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c: Leverage DEF_AVG_0_WRAP to generate the correct func name. * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: Ditto. Signed-off-by: Pan Li <pan2...@intel.com> Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c index 138124c8c4a0..31d3b43de049 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int32_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c index 30438c90abea..7f30b9ec3f16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c index 2e9cfa509403..2e06d0a3a464 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c @@ -6,7 +6,7 @@ #define NT int32_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c index 64df06b27e9b..ca2306627502 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c @@ -6,7 +6,7 @@ #define NT int64_t #define WT int128_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c index 2ebf2945a0ee..dda84a6b4379 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int16_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c index 64fec9135b5d..dfd2bb31357e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int32_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c index a72642c9b103..d1060cc663db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c index 16ba96735000..fc7943c5e21e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int32_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c index b229b4b5703a..e02e5df69c47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c index 5f946bbc8cd4..e36e4242cb0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c @@ -6,7 +6,7 @@ #define NT int32_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c index c94dfc2bde21..3e2d97ddad4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c @@ -6,7 +6,7 @@ #define NT int64_t #define WT int128_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c index 5d9297a6c394..cdbb2999183a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int16_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c index 5c5d4ea40bb1..53508b09ac39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int32_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c index f297953aadf4..9a6d1a21e52f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */