https://gcc.gnu.org/g:7a3b7a149d5fd5398a989fc713ba13ab16a6f858
commit 7a3b7a149d5fd5398a989fc713ba13ab16a6f858
Author: Surya Kumari Jangala <jskum...@linux.ibm.com>
Date: Mon Jul 14 22:33:44 2025 -0500
MMA+: Change __dmr to __dmr1024
This patch makes all the changes necessary to support __dmr1024 type.
Tests have been changed too. This patch also removes
dg-require-effective-target in the test dm-1024bit.c
Diff:
---
gcc/config/rs6000/mma.md | 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 +-
gcc/config/rs6000/rs6000-gen-builtins.cc | 2 +-
gcc/config/rs6000/rs6000-modes.def | 2 +-
gcc/config/rs6000/rs6000.cc | 12 ++---
gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 17 +++---
gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c | 60 +++++++++++-----------
.../gcc.target/powerpc/dmf-disassemble-dmr.c | 2 +-
gcc/testsuite/gcc.target/powerpc/dmf-extract512.c | 2 +-
10 files changed, 52 insertions(+), 53 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index a4ae785171ca..c7ec9d0fb56d 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -861,7 +861,7 @@
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-;; TDOmode (__dmr keyword for 1,024 bit registers).
+;; TDOmode (__dmr1024 keyword for 1,024 bit registers).
(define_expand "movtdo"
[(set (match_operand:TDO 0 "nonimmediate_operand")
(match_operand:TDO 1 "input_operand"))]
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index a27499d20a65..d675bee1e91a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -513,7 +513,7 @@ const char *rs6000_type_string (tree type_node)
else if (type_node == vector_quad_type_node)
return "__vector_quad";
else if (type_node == dmr_type_node)
- return "__dmr";
+ return "__dmr1024";
return "unknown";
}
@@ -811,7 +811,7 @@ rs6000_init_builtins (void)
TYPE_SIZE_UNIT (dmr_type_node) = size_int (GET_MODE_SIZE (TDOmode));
SET_TYPE_ALIGN (dmr_type_node, 512);
TYPE_USER_ALIGN (dmr_type_node) = 0;
- lang_hooks.types.register_builtin_type (dmr_type_node, "__dmr");
+ lang_hooks.types.register_builtin_type (dmr_type_node, "__dmr1024");
t = build_qualified_type (dmr_type_node, TYPE_QUAL_CONST);
ptr_dmr_type_node = build_pointer_type (t);
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/config/rs6000/rs6000-gen-builtins.cc
index 45f4362feaad..2c7bb44102e7 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -1077,7 +1077,7 @@ match_type (typeinfo *typedata, int voidok)
vd vector double
v256 __vector_pair
v512 __vector_quad
- dm1024 __dmr
+ dm1024 __dmr1024
For simplicity, We don't support "short int" and "long long int".
We don't currently support a <basetype> of "_Float16". "signed"
diff --git a/gcc/config/rs6000/rs6000-modes.def
b/gcc/config/rs6000/rs6000-modes.def
index f7f950b5837b..93e12a9c6dcc 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -80,6 +80,6 @@ PARTIAL_INT_MODE (TI, 128, PTI);
OPAQUE_MODE (OO, 32);
OPAQUE_MODE (XO, 64);
-/* Mode used by __dmr. */
+/* Mode used by __dmr1024. */
OPAQUE_MODE (TDO, 128);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 73eda16af415..54aa17ffc46f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -11353,7 +11353,7 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode
mode)
case E_TDOmode:
if (CONST_INT_P (operands[1]))
error ("%qs is an opaque type, and you cannot set it to constants",
- "__dmr");
+ "__dmr1024");
break;
case E_SImode:
@@ -20808,7 +20808,7 @@ rs6000_mangle_type (const_tree type)
if (type == vector_quad_type_node)
return "u13__vector_quad";
if (type == dmr_type_node)
- return "u5__dmr";
+ return "u5__dmr1024";
/* For all other types, use the default mangling. */
return NULL;
@@ -22939,7 +22939,7 @@ rs6000_dmr_register_move_cost (machine_mode mode,
reg_class_t rclass)
if (mode == XOmode)
return reg_move_base;
- /* __dmr (i.e. TDOmode) is transferred in 2 instructions. */
+ /* __dmr1024 (i.e. TDOmode) is transferred in 2 instructions. */
else if (mode == TDOmode)
return reg_move_base * 2;
@@ -27840,7 +27840,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
return;
}
- /* The __vector_pair, __vector_quad, and __dmr modes are multi-register
+ /* The __vector_pair, __vector_quad, and __dmr1024 modes are multi-register
modes, so if we have to load or store the registers, we have to be careful
to properly swap them if we're in little endian mode below. This means
the last register gets the first memory location. We also need to be
@@ -29150,9 +29150,9 @@ rs6000_invalid_conversion (const_tree fromtype,
const_tree totype)
if (tomode == OOmode)
return N_("invalid conversion to type %<__vector_pair%>");
if (frommode == TDOmode)
- return N_("invalid conversion from type %<__dmr%>");
+ return N_("invalid conversion from type %<__dmr1024%>");
if (tomode == TDOmode)
- return N_("invalid conversion to type %<__dmr%>");
+ return N_("invalid conversion to type %<__dmr1024%>");
}
/* Conversion allowed. */
diff --git a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
b/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
index 0a9884ddf637..0b36763ad675 100644
--- a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
+++ b/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
@@ -1,8 +1,7 @@
/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_dense_math_ok } */
/* { dg-options "-mdejagnu-cpu=future -O2" } */
-/* Test basic load/store for __dmr type. */
+/* Test basic load/store for __dmr1024 type. */
#ifndef CONSTRAINT
#if defined(USE_D)
@@ -20,10 +19,10 @@
#endif
const char constraint[] = CONSTRAINT;
-void foo_mem_asm (__dmr *p, __dmr *q)
+void foo_mem_asm (__dmr1024 *p, __dmr1024 *q)
{
/* 2 LXVP instructions. */
- __dmr vq = *p;
+ __dmr1024 vq = *p;
/* 2 DMXXINSTDMR512 instructions to transfer VSX to DMR. */
__asm__ ("# foo (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq));
@@ -33,12 +32,12 @@ void foo_mem_asm (__dmr *p, __dmr *q)
*q = vq;
}
-void foo_mem_asm2 (__dmr *p, __dmr *q)
+void foo_mem_asm2 (__dmr1024 *p, __dmr1024 *q)
{
/* 2 LXVP instructions. */
- __dmr vq = *p;
- __dmr vq2;
- __dmr vq3;
+ __dmr1024 vq = *p;
+ __dmr1024 vq2;
+ __dmr1024 vq3;
/* 2 DMXXINSTDMR512 instructions to transfer VSX to DMR. */
__asm__ ("# foo1 (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq));
@@ -51,7 +50,7 @@ void foo_mem_asm2 (__dmr *p, __dmr *q)
*q = vq2;
}
-void foo_mem (__dmr *p, __dmr *q)
+void foo_mem (__dmr1024 *p, __dmr1024 *q)
{
/* 2 LXVP, 2 STXVP instructions, no DMR transfer. */
*q = *p;
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
b/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
index a3f908efd432..c7516fdb10ad 100644
--- a/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-build-dmr.c
@@ -4,7 +4,7 @@
typedef unsigned char vec_t __attribute__((vector_size(16)));
void
-foo2 (__dmr *dst, vec_t *src)
+foo2 (__dmr1024 *dst, vec_t *src)
{
__builtin_mma_build_dmr (dst, src[0], src[1], src[2], src[3], src[4],
src[5], src[6], src[7]);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
b/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
index d45a19b1a684..9f66890055a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
@@ -4,9 +4,9 @@
typedef unsigned char vec_t __attribute__((vector_size(16)));
void
-foo (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -15,9 +15,9 @@ foo (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvbf16gerx2 (&dmr, vp, vec);
@@ -27,9 +27,9 @@ bar (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2\M} 2 } } */
void
-foo_1 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_1 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -38,9 +38,9 @@ foo_1 (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar_1 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar_1 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvbf16gerx2nn (&dmr, vp, vec);
@@ -50,9 +50,9 @@ bar_1 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2nn\M} 2 } } */
void
-foo_2 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_2 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -61,9 +61,9 @@ foo_2 (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar_2 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar_2 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvbf16gerx2np (&dmr, vp, vec);
@@ -73,9 +73,9 @@ bar_2 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2np\M} 2 } } */
void
-foo_3 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_3 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -84,9 +84,9 @@ foo_3 (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar_3 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar_3 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvbf16gerx2pn (&dmr, vp, vec);
@@ -96,9 +96,9 @@ bar_3 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2pn\M} 2 } } */
void
-foo_4 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_4 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -107,9 +107,9 @@ foo_4 (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar_4 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar_4 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvbf16gerx2pp (&dmr, vp, vec);
@@ -119,7 +119,7 @@ bar_4 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2pp\M} 2 } } */
void
-foo_5 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_5 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -129,7 +129,7 @@ foo_5 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2\M} 1 } } */
void
-foo_6 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_6 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -139,7 +139,7 @@ foo_6 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2nn\M} 1 } } */
void
-foo_7 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_7 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -149,7 +149,7 @@ foo_7 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2np\M} 1 } } */
void
-foo_8 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_8 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -159,7 +159,7 @@ foo_8 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2pn\M} 1 } } */
void
-foo_9 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_9 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -169,7 +169,7 @@ foo_9 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2pp\M} 1 } } */
void
-foo_10 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_10 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
__vector_pair vp = *vpp;
vec_t vec = *src;
@@ -179,9 +179,9 @@ foo_10 (__dmr *dst, __vector_pair *vpp, vec_t *src)
/* { dg-final { scan-assembler-times {\mpmdmxvi8gerx4spp\M} 1 } } */
void
-foo_11 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+foo_11 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr;
+ __dmr1024 dmr;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmsetdmrz (&dmr);
@@ -190,9 +190,9 @@ foo_11 (__dmr *dst, __vector_pair *vpp, vec_t *src)
}
void
-bar_11 (__dmr *dst, __vector_pair *vpp, vec_t *src)
+bar_11 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
{
- __dmr dmr = dst[0];;
+ __dmr1024 dmr = dst[0];;
__vector_pair vp = *vpp;
vec_t vec = *src;
__builtin_mma_dmxvi8gerx4spp (&dmr, vp, vec);
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-disassemble-dmr.c
b/gcc/testsuite/gcc.target/powerpc/dmf-disassemble-dmr.c
index b1406ec380e1..8e9adf6887a1 100644
--- a/gcc/testsuite/gcc.target/powerpc/dmf-disassemble-dmr.c
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-disassemble-dmr.c
@@ -4,7 +4,7 @@
typedef unsigned char vec_t __attribute__((vector_size(16)));
void
-bar (vec_t *dst, __dmr *src)
+bar (vec_t *dst, __dmr1024 *src)
{
vec_t res[8];
__builtin_mma_disassemble_dmr (res, src);
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-extract512.c
b/gcc/testsuite/gcc.target/powerpc/dmf-extract512.c
index 17757898b579..865174f57206 100644
--- a/gcc/testsuite/gcc.target/powerpc/dmf-extract512.c
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-extract512.c
@@ -4,7 +4,7 @@
typedef unsigned char vec_t __attribute__((vector_size(16)));
void
-bar (vec_t *dst, __dmr *src)
+bar (vec_t *dst, __dmr1024 *src)
{
vec_t res[4];
__builtin_mma_dmr_extract512 (res, src, 0);
