https://gcc.gnu.org/g:f01216a0b71a3e88c796ed302d6a6bc2fdb35d44
commit r16-2234-gf01216a0b71a3e88c796ed302d6a6bc2fdb35d44
Author: Pan Li <pan2...@intel.com>
Date: Fri Jul 11 08:38:09 2025 +0800
Match: Refine the widen mul check for SAT_MUL pattern
The widen mul will have source type from N-bits to
dest type 2N-bits. The previous check only focus on
the HOST_WIDE_INT but not working for QI => HI, HI => SI
and SI to DImode. Thus, refine the widen mul precision
check as dest has twice bits of input.
gcc/ChangeLog:
* match.pd: Make sure widen mul has twice bitsize
of the inputs in SAT_MUL pattern.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
gcc/match.pd | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index 67b33eee5f79..7f84d5149f42 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3605,11 +3605,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
unsigned widen_prec = TYPE_PRECISION (TREE_TYPE (@3));
unsigned cvt5_prec = TYPE_PRECISION (TREE_TYPE (@5));
unsigned cvt6_prec = TYPE_PRECISION (TREE_TYPE (@6));
- unsigned hw_int_prec = sizeof (HOST_WIDE_INT) * 8;
wide_int c2 = wi::to_wide (@2);
wide_int max = wi::mask (prec, false, widen_prec);
bool c2_is_max_p = wi::eq_p (c2, max);
- bool widen_mult_p = cvt5_prec == cvt6_prec && hw_int_prec == cvt5_prec;
+ bool widen_mult_p = cvt5_prec == cvt6_prec && widen_prec == cvt6_prec *
2;
}
(if (widen_prec > prec && c2_is_max_p && widen_mult_p)))))
)
