The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
5159c19cb2a8... [RISC-V] Fix ICE due to bogus use of gen_rtvec
It previously pointed to:
e968c7311c62... Alpha: Fix base block alignment calculation regression
Diff:
Summary of changes (added commits):
-----------------------------------
5159c19... [RISC-V] Fix ICE due to bogus use of gen_rtvec
8010f98... [RISC-V] Avoid setting output object more than once in IOR/
99d801c... RISC-V: Since the loop increment i++ is unreachable, the lo
6e73320... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
84adfa2... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
49278dd... Make end_sequence return the insn sequence
9a8ca2f... RISC-V: Reuse test name for vx combine test data [NFC]
76ecd76... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
13a6e9f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
1a93ea8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
04f07ee... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
c0cb19a... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
7195b88... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
8776c19... RISC-V: Adjust vx combine test case to avoid name conflict
f6ae7c8... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
6785ad3... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
103da6a... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
5e6cb89... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
fa7576e... RISC-V: Add augmented hypervisor series extensions.
b0fb9ba... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
a4d3735... RISC-V: Regen riscv-ext.opt.urls
8b77ff6... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
1931c49... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
d5d13d9... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
1c2a373... RISC-V: Introduce riscv_ext_info_t to hold extension metada
4d7dafb... RISC-V: Adjust riscv_can_inline_p
ac1cfc5... RISC-V: Generate extension table in documentation from risc
dff806e... RISC-V: Use riscv-ext.def to generate target options and va
f63e8d3... RISC-V: Introduce riscv-ext*.def to define extensions
194d03f... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
24f53c2... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
9df770e... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
543db94... RISC-V: Support for zilsd and zclsd extensions.
e63c207... testsuite: Fix RISC-V arch-52.c format issue.
e887f88... RISC-V: Support RISC-V Profiles 23.
7f87d18... RISC-V: Support RISC-V Profiles 20/22.
7866e62... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
ea263e8... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
c118441... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
621d370... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
1072dae... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
3045c15... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
e6cdd98... RISC-V: Separate the test running of rvv vx_vf
8ad5762... [RISC-V][PR target/120137][PR target/120154] Don't create o
1953b5e... [PATCH] RISC-V: Minimal support for zama16b extension.
832d5bc... [RISC-V] Avoid unnecessary andi with -1 argument
71b1760... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
a67f729... [PATCH] RISC-V: Recognized svadu and svade extension
65d4610... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
9d9135a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
11b0993... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
39e8197... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
c5d906d... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
2ee71e5... RISC-V: Add gr2vr cost helper function
9b6166d... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
f792a2e... [RISC-V][PR target/119971] Avoid losing shift count masking
b4ff83a... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
6b9a261... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
10057e3... [V2][RISC-V] Trivial permutation constant derivation
1cc79df... [RISC-V] Adjust rvv tests after recent jump threading chang
f597a59... [PATCH] RISC-V: Implment H modifier for printing the next r
f7d0410... [to-be-committed][RISC-V] Adjust testcases and finish regis
1982909... RISC-V: Remove unnecessary frm restore volatile define_insn
5179fed... RISC-V: Allow different dynamic floating point mode to be m
5561ed0... RISC-V: Fix missing implied Zicsr from Zve32x
2e800ed... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
8633535... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
2bf7f42... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
f789cda... RISC-V: Extract vector stepped for expand_const_vector [NFC
11dcc49... RISC-V: Extract vector duplicate for expand_const_vector [N
8146b6e... RISC-V: Extract vec_series for expand_const_vector [NFC]
84be3be... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
e7e5a11... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
3cbe409... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
9849e5f... [riscv] vec_dup immediate constants in pred_broadcast expan
f8d5c0a... [RISC-V][PR target/119865] Don't free ggc allocated memory
512a79e... [RISC-V][PR target/118410] Improve code generation for some
9c84211... [RISC-V] Fix missed bext discovery
dd04c59... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
ec8bf88... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
8b34e03... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
4ed1879... Daily bump. (*)
9fa72d7... Update cpplib es.po (*)
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