https://gcc.gnu.org/g:dce8782607a399ce969b31fa1e4bea426d93359f
commit dce8782607a399ce969b31fa1e4bea426d93359f
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Apr 3 17:00:13 2025 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.paddis | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/gcc/ChangeLog.paddis b/gcc/ChangeLog.paddis
index ef499f386bcd..b25d549f9637 100644
--- a/gcc/ChangeLog.paddis
+++ b/gcc/ChangeLog.paddis
@@ -1,5 +1,150 @@
+==================== Branch work199-paddis, patch #311 ====================
+
+RFC2677-Add xvrlw support.
+
+2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/altivec.md (xvrlw): New insn.
+ * config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vector-rotate-left.c: New test.
+
+==================== Branch work199-paddis, patch #310 ====================
+
+RFC2686-Add paddis support.
+
+2025-04-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/constraints.md (eU): New constraint.
+ (eV): Likewise.
+ * config/rs6000/predicates.md (paddis_operand): New predicate.
+ (paddis_paddi_operand): Likewise.
+ (add_operand): Add paddis support.
+ * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support.
+ (num_insns_constant_multi): Likewise.
+ (print_operand): Add %B<n> for paddis support.
+ * config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
+ (SIGNED_INTEGER_32BIT_P): Likewise.
+ * config/rs6000/rs6000.md (isa attribute): Add paddis support.
+ (enabled attribute); Likewise.
+ (add<mode>3): Likewise.
+ (adddi3 splitter): New splitter for paddis.
+ (movdi_internal64): Add paddis support.
+ (movdi splitter): New splitter for paddis.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/prefixed-addis.c: New test.
+
+==================== Branch work199-paddis, patch #301 ====================
+
+RFC2655-Add saturating subtract built-ins.
+
+This patch adds support for a saturating subtract built-in function that may be
+added to a future PowerPC processor. Note, if it is added, the name of the
+built-in function may change before GCC 13 is released. If the name changes,
+we will submit a patch changing the name.
+
+I also added support for providing dense math built-in functions, even though
+at present, we have not added any new built-in functions for dense math. It is
+likely we will want to add new dense math built-in functions as the dense math
+support is fleshed out.
+
+The patches have been tested on both little and big endian systems. Can I
check
+it into the master branch?
+
+2025-03-27 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support
+ for flagging invalid use of future built-in functions.
+ (rs6000_builtin_is_supported): Add support for future built-in
+ functions.
+ * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New
+ built-in function for -mcpu=future.
+ (__builtin_saturate_subtract64): Likewise.
+ * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas
+ for -mcpu=future built-ins.
+ (stanza_map): Likewise.
+ (enable_string): Likewise.
+ (struct attrinfo): Likewise.
+ (parse_bif_attrs): Likewise.
+ (write_decls): Likewise.
+ * config/rs6000/rs6000.md (sat_sub<mode>3): Add saturating subtract
+ built-in insn declarations.
+ (sat_sub<mode>3_dot): Likewise.
+ (sat_sub<mode>3_dot2): Likewise.
+ * doc/extend.texi (Future PowerPC built-ins): New section.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/subfus-1.c: New test.
+ * gcc.target/powerpc/subfus-2.c: Likewise.
+
+==================== Branch work199-paddis, patch #300 ====================
+
+RFC2656-Support load/store vector with right length.
+
+This patch adds support for new instructions that may be added to the PowerPC
+architecture in the future to enhance the load and store vector with length
+instructions.
+
+The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use
+since the count for the number of bytes must be in the top 8 bits of the GPR
+register, instead of the bottom 8 bits. This meant that code generating these
+instructions typically had to do a shift left by 56 bits to get the count into
+the right position. In a future version of the PowerPC architecture, new
+variants of these instructions might be added that expect the count to be in
+the bottom 8 bits of the GPR register. These patches add this support to GCC
+if the user uses the -mcpu=future option.
+
+I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl
+future lxvll/stxvll instructions would generate these instructions on 32-bit.
+However the patterns for these instructions is only done on 64-bit systems. So
+I added a check for 64-bit support before generating the instructions.
+
+The patches have been tested on both little and big endian systems. Can I
check
+it into the master branch?
+
+2025-04-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-string.cc (expand_block_move): Do not generate
+ lxvl and stxvl on 32-bit.
+ * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with
+ the shift count automaticaly used in the insn.
+ (lxvrl): New insn for -mcpu=future.
+ (lxvrll): Likewise.
+ (stxvl): If -mcpu=future, generate the stxvl with the shift count
+ automaticaly used in the insn.
+ (stxvrl): New insn for -mcpu=future.
+ (stxvrll): Likewise.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/lxvrl.c: New test.
+ * lib/target-supports.exp (check_effective_target_powerpc_future_ok):
+ New effective target.
+
==================== Branch work199-paddis, baseline ====================
+Add ChangeLog.paddis and update REVISION.
+
+2025-04-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.paddis: New file for branch.
+ * REVISION: Update.
+
2025-04-03 Michael Meissner <meiss...@linux.ibm.com>
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