https://gcc.gnu.org/g:5ba6fdc5476d33c57f4751cae93054fdbc7211c0
commit r14-11443-g5ba6fdc5476d33c57f4751cae93054fdbc7211c0
Author: Haochen Jiang <haochen.ji...@intel.com>
Date: Mon Mar 24 15:51:16 2025 +0800
i386: Add -mavx10.1 back with 512 bit alias
When AVX10.1 options are added into GCC 14, E-core is supposed to
support up to 256 bit vector width, while P-core up to 512 bit vector
width. Therefore, we added avx10.1-256 and avx10.1-512 options into
compiler and alias avx10.1 to 256 bit for compatibility since there
will be real platforms with 256 bit only support.
However, all the future platforms will now support 512 bit vector width,
including P-core and E-core. Therefore, we could alias avx10.1 directly
to 512 bit. However, avx10.1 alias to 256 bit has been there in GCC 14.1
and GCC 14.2, so we have to raise a warning since GCC 14.3 for this
behavior change.
While backporting the patch from GCC 15, we choose to only warn when
users use -mavx10.1 option in order not to interrupt the usage of other
options since -mavx10.1-256/512 and -mevex512 will be dropped in GCC 16.
There is no need to warn them this early in GCC 14 to overwhelm users.
gcc/ChangeLog:
* common/config/i386/i386-isas.h: Add avx10.1.
* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.opt: Ditto.
* config/i386/i386.opt.urls: Ditto.
* doc/extend.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
Diff:
---
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config/i386/i386-c.cc | 5 +----
gcc/config/i386/i386-options.cc | 1 +
gcc/config/i386/i386.opt | 5 +++++
gcc/config/i386/i386.opt.urls | 3 +++
gcc/doc/extend.texi | 6 ++++++
gcc/doc/sourcebuild.texi | 3 +++
7 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index 017c795e211d..cdbc188620ad 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -195,4 +195,5 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256,
"-mavx10.1-256")
ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512,
"-mavx10.1-512")
+ ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_512, P_AVX10_1_512,
"-mavx10.1")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 07f4936ba910..0103b8543a15 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -743,10 +743,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR)
def_or_undef (parse_in, "__USER_MSR__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256)
- {
- def_or_undef (parse_in, "__AVX10_1_256__");
- def_or_undef (parse_in, "__AVX10_1__");
- }
+ def_or_undef (parse_in, "__AVX10_1_256__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_512)
def_or_undef (parse_in, "__AVX10_1_512__");
if (isa_flag2 & OPTION_MASK_ISA2_APX_F)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 11c6ddf0f440..57c83a9aa1c7 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1137,6 +1137,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("usermsr", OPT_musermsr),
IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
+ IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_512),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index f99c4e3ae5d9..df95963dd9f0 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1380,3 +1380,8 @@ mavx10.1-512
Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
and AVX10.1-512 built-in functions and code generation.
+
+mavx10.1
+Target Alias(mavx10.1-512) Warn(%<-mavx10.1%> is aliased to 512 bit since
GCC14.3)
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1-512 built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 3ed766350020..81c5bb9a9270 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -615,3 +615,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256)
mavx10.1-512
UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512)
+mavx10.1
+UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1)
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 8bd30bb2a468..27fefb30041e 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7395,6 +7395,12 @@ Disable the generation of the AVX10.1 instructions.
Enable the generation of the AVX10.1 instructions with 512 bit support.
Disable the generation of the AVX10.1 instructions.
+@cindex @code{target("avx10.1")} function attribute, x86
+@item avx10.1
+@itemx no-avx10.1
+Enable the generation of the AVX10.1 instructions with 512 bit support.
+Disable the generation of the AVX10.1 instructions.
+
@cindex @code{target("cld")} function attribute, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 5b026cfe073e..23dedef41619 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2549,6 +2549,9 @@ Target supports the execution of @code{avx10.1-256}
instructions.
@item avx10.1-512
Target supports the execution of @code{avx10.1-512} instructions.
+@item avx10.1
+Target supports the execution of @code{avx10.1} instructions.
+
@item avx2
Target supports compiling @code{avx2} instructions.
