https://gcc.gnu.org/g:12b7220dc5beafaf9c738b473e046ed66e49a52a
commit r15-7199-g12b7220dc5beafaf9c738b473e046ed66e49a52a
Author: Andrew Carlotti <andrew.carlo...@arm.com>
Date: Fri Jan 24 11:00:41 2025 +0000
aarch64: Add +cpa feature flag
This doesn't enable anything within the compiler, but this allows the
flag to be passed the assembler. There also doesn't appear to be a
kernel cpuinfo name yet.
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
* config/aarch64/aarch64-option-extensions.def (CPA): New.
* doc/invoke.texi: Document +cpa.
Diff:
---
gcc/config/aarch64/aarch64-arches.def | 2 +-
gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
gcc/doc/invoke.texi | 4 +++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-arches.def
b/gcc/config/aarch64/aarch64-arches.def
index dacb7b6f37a3..34a792d69510 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -46,6 +46,6 @@ AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A,
9, (V8_6A, V9A))
AARCH64_ARCH("armv9.2-a", generic_armv9_a, V9_2A, 9, (V8_7A, V9_1A))
AARCH64_ARCH("armv9.3-a", generic_armv9_a, V9_3A, 9, (V8_8A, V9_2A))
AARCH64_ARCH("armv9.4-a", generic_armv9_a, V9_4A, 9, (V8_9A, V9_3A))
-AARCH64_ARCH("armv9.5-a", generic_armv9_a, V9_5A, 9, (V9_4A,
FAMINMAX, LUT))
+AARCH64_ARCH("armv9.5-a", generic_armv9_a, V9_5A, 9, (V9_4A, CPA,
FAMINMAX, LUT))
#undef AARCH64_ARCH
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index a1133accfce5..cc42bd518dca 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -275,6 +275,8 @@ AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2,
(SSVE_FP8DOT4), (), (), "sme
AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
+AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
+
#undef AARCH64_OPT_FMV_EXTENSION
#undef AARCH64_OPT_EXTENSION
#undef AARCH64_FMV_FEATURE
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c8721064f91e..dddde54a287d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21672,7 +21672,7 @@ and the features that they enable by default:
@item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+wfxt},
@samp{+xs}
@item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops}
@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a}
-@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{+faminmax},
@samp{+lut}
+@item @samp{armv9.5-a} @tab Armv9.4-A @tab @samp{armv9.4-a}, @samp{cpa},
@samp{+faminmax}, @samp{+lut}
@item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r}
@end multitable
@@ -22085,6 +22085,8 @@ extension in streaming mode.
Enable the Floating Point Absolute Maximum/Minimum extension.
@item lut
Enable the Lookup Table extension.
+@item cpa
+Enable the Checked Pointer Arithmetic instructions.
@item sve-b16b16
Enable the SVE non-widening brain floating-point (@code{bf16}) extension.
This only has an effect when @code{sve2} or @code{sme2} are also enabled.
