https://gcc.gnu.org/g:cc6176a921cbe3b9db323b1cd557efe4f299171a
commit r15-7011-gcc6176a921cbe3b9db323b1cd557efe4f299171a
Author: Xi Ruoyao <xry...@xry111.site>
Date: Fri Sep 6 03:27:19 2024 +0800
LoongArch: Add alsl.wu
On 64-bit capable LoongArch hardware, alsl.wu is similar to alsl.w but
zero-extending the 32-bit result.
gcc/ChangeLog:
* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/alsl_wu.c: New test.
Diff:
---
gcc/config/loongarch/loongarch.md | 8 ++++----
gcc/testsuite/gcc.target/loongarch/alsl_wu.c | 9 +++++++++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 59f457703110..1b46e8e4af0d 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3143,15 +3143,15 @@
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
-(define_insn "alslsi3_extend"
+(define_insn "*alslsi3_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI
+ (any_extend:DI
(plus:SI
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "const_immalsl_operand" ""))
(match_operand:SI 3 "register_operand" "r"))))]
- ""
- "alsl.w\t%0,%1,%3,%2"
+ "TARGET_64BIT"
+ "alsl.w<u>\t%0,%1,%3,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
diff --git a/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
new file mode 100644
index 000000000000..65f55e629ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2" } */
+/* { dg-final { scan-assembler "alsl\\.wu" } } */
+
+unsigned long
+test (unsigned int a, unsigned int b)
+{
+ return (a << 2) + b;
+}
