https://gcc.gnu.org/g:8efff8e6bb1765c6dd3aba1a38667b8f77326f58
commit 8efff8e6bb1765c6dd3aba1a38667b8f77326f58
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Jan 16 12:20:58 2025 -0500
Change TARGET_POPCNTD to TARGET_POWER7.
This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch
is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.6 (Power7).
2025-01-16 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/dfp.md (cmp<mode>_internal1): Change
TARGET_POPCNTD
to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare):
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_POWER7): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(lrint<mode>si2): Likewise.
(lrint<mode>si): Likewise.
(lrint<mode>si_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_<mode>): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div<div_extend>_<mode>): Likewise.
Diff:
---
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 8 ++++----
gcc/config/rs6000/rs6000.h | 21 +++++++++++----------
gcc/config/rs6000/rs6000.md | 20 ++++++++++----------
6 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 59fa66ae15c8..5919149682b2 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POPCNTD"
+ "TARGET_DFP && TARGET_POWER7"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index dbb8520ab039..2366b2aee00a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P6_64:
return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POPCNTD;
+ return TARGET_POWER7;
case ENB_P7_64:
- return TARGET_POPCNTD && TARGET_POWERPC64;
+ return TARGET_POWER7 && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 3d2911ca08a0..703f77fa0bf1 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POPCNTD);
+ gcc_assert (TARGET_POWER7);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d2814364b3d0..1bba77244c25 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1924,7 +1924,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3918,7 +3918,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POPCNTD)
+ else if (TARGET_POWER7)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
@@ -4131,7 +4131,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
{
if (global_options.x_rs6000_ieeequad
- && (!TARGET_POPCNTD || !TARGET_VSX))
+ && (!TARGET_POWER7 || !TARGET_VSX))
error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT)
@@ -22373,7 +22373,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case POPCOUNT:
- *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
return false;
case PARITY:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 62e1662d078a..856d268d2d27 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -442,7 +442,7 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
@@ -450,17 +450,17 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POPCNTD) /* ISA 2.06 */
+ || TARGET_POWER7) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
#define TARGET_LFIWAX TARGET_POWER6
-#define TARGET_LFIWZX TARGET_POPCNTD
-#define TARGET_FCFIDS TARGET_POPCNTD
-#define TARGET_FCFIDU TARGET_POPCNTD
-#define TARGET_FCFIDUS TARGET_POPCNTD
-#define TARGET_FCTIDUZ TARGET_POPCNTD
-#define TARGET_FCTIWUZ TARGET_POPCNTD
+#define TARGET_LFIWZX TARGET_POWER7
+#define TARGET_FCFIDS TARGET_POWER7
+#define TARGET_FCFIDU TARGET_POWER7
+#define TARGET_FCFIDUS TARGET_POWER7
+#define TARGET_FCTIDUZ TARGET_POWER7
+#define TARGET_FCTIWUZ TARGET_POWER7
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
#define TARGET_CTZ TARGET_MODULO
@@ -503,6 +503,7 @@ extern int rs6000_vector_align[];
#define TARGET_POWER5 TARGET_POPCNTB
#define TARGET_POWER5X TARGET_FPRND
#define TARGET_POWER6 TARGET_CMPB
+#define TARGET_POWER7 TARGET_POPCNTD
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx>
@@ -532,7 +533,7 @@ extern int rs6000_vector_align[];
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
+ || TARGET_POWER7 /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -1740,7 +1741,7 @@ typedef struct rs6000_args
zero. The hardware instructions added in Power9 and the sequences using
popcount return 32 or 64. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- (TARGET_CTZ || TARGET_POPCNTD
\
+ (TARGET_CTZ || TARGET_POWER7 \
? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
: ((VALUE) = -1, 2))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7382bdb4da79..87ec37a9f8e4 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -387,7 +387,7 @@
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POPCNTD"))
+ (match_test "TARGET_POWER7"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -6786,7 +6786,7 @@
/* For those old archs in which SImode can't be hold in float registers,
call lrint<mode>si_di to put the result in DImode then convert it via
stack. */
- if (!TARGET_POPCNTD)
+ if (!TARGET_POWER7)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6801,7 +6801,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POPCNTD"
+ "TARGET_HARD_FLOAT && TARGET_POWER7"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6809,7 +6809,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
+ "TARGET_HARD_FLOAT && !TARGET_POWER7"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -10173,7 +10173,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14440,7 +14440,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14818,7 +14818,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14826,7 +14826,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14834,7 +14834,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14849,7 +14849,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POPCNTD"
+ "TARGET_POWER7"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
