https://gcc.gnu.org/g:6f7626f7a7a7460158c4d55363df81ca4087000c
commit r15-6182-g6f7626f7a7a7460158c4d55363df81ca4087000c
Author: John David Anglin <dang...@gcc.gnu.org>
Date: Thu Dec 12 15:22:22 2024 -0500
hppa: Remove extra clobber from divsi3, udivsi3, modsi3 and umodsi3 patterns
The $$divI, $$divU, $$remI and $$remU millicode calls clobber r1,
r26, r25 and the return link register (r31 or r2). We don't need
to clobber any other registers.
2024-12-12 John David Anglin <dang...@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa.cc (pa_emit_hpdiv_const): Clobber r1, r25,
r25 and return register.
* config/pa/pa.md (divsi3): Revise clobbers and operands.
Remove second clobber from div:SI insns.
(udivsi3, modsi3, umodsi3): Likewise.
Diff:
---
gcc/config/pa/pa.cc | 5 ++--
gcc/config/pa/pa.md | 81 +++++++++--------------------------------------------
2 files changed, 16 insertions(+), 70 deletions(-)
diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 776cb1ffa24a..99ed2863eb9f 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -6159,13 +6159,12 @@ pa_emit_hpdiv_const (rtx *operands, int unsignedp)
emit
(gen_rtx_PARALLEL
(VOIDmode,
- gen_rtvec (6, gen_rtx_SET (gen_rtx_REG (SImode, 29),
+ gen_rtvec (5, gen_rtx_SET (gen_rtx_REG (SImode, 29),
gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
SImode,
gen_rtx_REG (SImode, 26),
operands[2])),
- gen_rtx_CLOBBER (VOIDmode, operands[4]),
- gen_rtx_CLOBBER (VOIDmode, operands[3]),
+ gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 1)),
gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
gen_rtx_CLOBBER (VOIDmode, ret))));
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 61447c0db5c5..352447272e06 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5738,27 +5738,16 @@
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
""
"
{
- operands[3] = gen_reg_rtx (SImode);
- if (TARGET_64BIT)
- {
- operands[5] = gen_rtx_REG (SImode, 2);
- operands[4] = operands[5];
- }
- else
- {
- operands[5] = gen_rtx_REG (SImode, 31);
- operands[4] = gen_reg_rtx (SImode);
- }
- if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
+ operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
+ if (pa_emit_hpdiv_const (operands, 0))
DONE;
}")
@@ -5766,7 +5755,6 @@
[(set (reg:SI 29)
(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
- (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5782,7 +5770,6 @@
[(set (reg:SI 29)
(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
- (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5798,28 +5785,16 @@
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
""
"
{
- operands[3] = gen_reg_rtx (SImode);
-
- if (TARGET_64BIT)
- {
- operands[5] = gen_rtx_REG (SImode, 2);
- operands[4] = operands[5];
- }
- else
- {
- operands[5] = gen_rtx_REG (SImode, 31);
- operands[4] = gen_reg_rtx (SImode);
- }
- if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
+ operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
+ if (pa_emit_hpdiv_const (operands, 1))
DONE;
}")
@@ -5827,7 +5802,6 @@
[(set (reg:SI 29)
(udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
- (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5843,7 +5817,6 @@
[(set (reg:SI 29)
(udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
(clobber (match_operand:SI 1 "register_operand" "=a"))
- (clobber (match_operand:SI 2 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5859,32 +5832,20 @@
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
""
"
{
- if (TARGET_64BIT)
- {
- operands[5] = gen_rtx_REG (SImode, 2);
- operands[4] = operands[5];
- }
- else
- {
- operands[5] = gen_rtx_REG (SImode, 31);
- operands[4] = gen_reg_rtx (SImode);
- }
- operands[3] = gen_reg_rtx (SImode);
+ operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
}")
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
- (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5899,7 +5860,6 @@
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
- (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
@@ -5915,32 +5875,20 @@
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
(parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
- (clobber (match_dup 3))
- (clobber (match_dup 4))
+ (clobber (reg:SI 1))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
- (clobber (match_dup 5))])
+ (clobber (match_dup 3))])
(set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
""
"
{
- if (TARGET_64BIT)
- {
- operands[5] = gen_rtx_REG (SImode, 2);
- operands[4] = operands[5];
- }
- else
- {
- operands[5] = gen_rtx_REG (SImode, 31);
- operands[4] = gen_reg_rtx (SImode);
- }
- operands[3] = gen_reg_rtx (SImode);
+ operands[3] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
}")
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
- (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
@@ -5955,7 +5903,6 @@
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (match_operand:SI 0 "register_operand" "=a"))
- (clobber (match_operand:SI 1 "register_operand" "=&r"))
(clobber (reg:SI 26))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
