https://gcc.gnu.org/g:57c2305f2ea7e631e2aad02f28606bbac2b7dd75
commit 57c2305f2ea7e631e2aad02f28606bbac2b7dd75
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon Dec 2 15:40:34 2024 -0500
RFC2653-PowerPC: Switch to dense math names for all MMA operations.
This patch changes the assembler instruction names for MMA instructions from
the original name used in power10 to the new name when used with the dense
math
system. I.e. xvf64gerpp becomes dmxvf64gerpp. The assembler will emit the
same bits for either spelling.
For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the
instruction. However, the prefixed instructions have a 'pm' prefix, and we
add
the 'dm' prefix afterwards. To prevent having two sets of parallel int
attributes, we remove the "pm" prefix from the instruction string in the
attributes, and add it later, both in the insn name and in the output
template.
2024-12-02 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/mma.md (vvi4i4i8): Change the instruction to not
have a
"pm" prefix.
(avvi4i4i8): Likewise.
(vvi4i4i2): Likewise.
(avvi4i4i2): Likewise.
(vvi4i4): Likewise.
(avvi4i4): Likewise.
(pvi4i2): Likewise.
(apvi4i2): Likewise.
(vvi4i4i4): Likewise.
(avvi4i4i4): Likewise.
(mma_<vv>): Add support for running on DMF systems, generating the
dense
math instruction and using the dense math accumulators.
(mma_<pv>): Likewise.
(mma_<avv>): Likewise.
(mma_<apv>): Likewise.
(mma_pm<vvi4i4i8>): Add support for running on DMF systems,
generating
the dense math instruction and using the dense math accumulators.
Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm'
prefixes based on whether we have the original MMA specification or
if
we have dense math support.
(mma_pm<avvi4i4i8>): Likewise.
(mma_pm<vvi4i4i2>): Likewise.
(mma_pm<avvi4i4i2>): Likewise.
(mma_pm<vvi4i4>): Likewise.
(mma_pm<avvi4i4): Likewise.
(mma_pm<pvi4i2>): Likewise.
(mma_pm<apvi4i2): Likewise.
(mma_pm<vvi4i4i4>): Likewise.
(mma_pm<avvi4i4i4>): Likewise.
Diff:
---
gcc/config/rs6000/mma.md | 157 +++++++++++++++++++++++++++++++----------------
1 file changed, 104 insertions(+), 53 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index ae6e7e9695be..2e04eb653fa6 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -225,44 +225,47 @@
(UNSPEC_MMA_XVF64GERNP "xvf64gernp")
(UNSPEC_MMA_XVF64GERNN "xvf64gernn")])
-(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
+;; The "pm" prefix is not in these expansions, so that we can generate
+;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems
+;; without dense math registers.
+(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")])
-(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP
"pmxvi4ger8pp")])
+(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "xvi4ger8pp")])
-(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2")
- (UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s")
- (UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2")
- (UNSPEC_MMA_PMXVBF16GER2
"pmxvbf16ger2")])
+(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "xvi16ger2")
+ (UNSPEC_MMA_PMXVI16GER2S "xvi16ger2s")
+ (UNSPEC_MMA_PMXVF16GER2 "xvf16ger2")
+ (UNSPEC_MMA_PMXVBF16GER2 "xvbf16ger2")])
-(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp")
- (UNSPEC_MMA_PMXVI16GER2SPP
"pmxvi16ger2spp")
- (UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp")
- (UNSPEC_MMA_PMXVF16GER2PN "pmxvf16ger2pn")
- (UNSPEC_MMA_PMXVF16GER2NP "pmxvf16ger2np")
- (UNSPEC_MMA_PMXVF16GER2NN "pmxvf16ger2nn")
- (UNSPEC_MMA_PMXVBF16GER2PP
"pmxvbf16ger2pp")
- (UNSPEC_MMA_PMXVBF16GER2PN
"pmxvbf16ger2pn")
- (UNSPEC_MMA_PMXVBF16GER2NP
"pmxvbf16ger2np")
- (UNSPEC_MMA_PMXVBF16GER2NN
"pmxvbf16ger2nn")])
+(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "xvi16ger2pp")
+ (UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp")
+ (UNSPEC_MMA_PMXVF16GER2PP "xvf16ger2pp")
+ (UNSPEC_MMA_PMXVF16GER2PN "xvf16ger2pn")
+ (UNSPEC_MMA_PMXVF16GER2NP "xvf16ger2np")
+ (UNSPEC_MMA_PMXVF16GER2NN "xvf16ger2nn")
+ (UNSPEC_MMA_PMXVBF16GER2PP "xvbf16ger2pp")
+ (UNSPEC_MMA_PMXVBF16GER2PN "xvbf16ger2pn")
+ (UNSPEC_MMA_PMXVBF16GER2NP "xvbf16ger2np")
+ (UNSPEC_MMA_PMXVBF16GER2NN
"xvbf16ger2nn")])
-(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER
"pmxvf32ger")])
+(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER
"xvf32ger")])
-(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp")
- (UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn")
- (UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp")
- (UNSPEC_MMA_PMXVF32GERNN
"pmxvf32gernn")])
+(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "xvf32gerpp")
+ (UNSPEC_MMA_PMXVF32GERPN "xvf32gerpn")
+ (UNSPEC_MMA_PMXVF32GERNP "xvf32gernp")
+ (UNSPEC_MMA_PMXVF32GERNN "xvf32gernn")])
-(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER
"pmxvf64ger")])
+(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER
"xvf64ger")])
-(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp")
- (UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn")
- (UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp")
- (UNSPEC_MMA_PMXVF64GERNN
"pmxvf64gernn")])
+(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "xvf64gerpp")
+ (UNSPEC_MMA_PMXVF64GERPN "xvf64gerpn")
+ (UNSPEC_MMA_PMXVF64GERNP "xvf64gernp")
+ (UNSPEC_MMA_PMXVF64GERNN "xvf64gernn")])
-(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")])
+(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "xvi8ger4")])
-(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp")
- (UNSPEC_MMA_PMXVI8GER4SPP
"pmxvi8ger4spp")])
+(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "xvi8ger4pp")
+ (UNSPEC_MMA_PMXVI8GER4SPP "xvi8ger4spp")])
;; Vector pair support. OOmode can only live in VSRs.
@@ -580,7 +583,9 @@
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
"TARGET_MMA"
- "<vv> %A0,%x1,%x2"
+{
+ return TARGET_DENSE_MATH ? "dm<vv> %A0,%x1,%x2" : "<vv> %A0,%x1,%x2";
+}
[(set_attr "type" "mma")])
(define_insn "mma_<avv>"
@@ -590,7 +595,9 @@
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
"TARGET_MMA"
- "<avv> %A0,%x2,%x3"
+{
+ return TARGET_DENSE_MATH ? "dm<avv> %A0,%x2,%x3" : "<avv> %A0,%x2,%x3";
+}
[(set_attr "type" "mma")])
(define_insn "mma_<pv>"
@@ -599,7 +606,9 @@
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
"TARGET_MMA"
- "<pv> %A0,%x1,%x2"
+{
+ return TARGET_DENSE_MATH ? "dm<pv> %A0,%x1,%x2" : "<pv> %A0,%x1,%x2";
+}
[(set_attr "type" "mma")])
(define_insn "mma_<apv>"
@@ -609,10 +618,12 @@
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
"TARGET_MMA"
- "<apv> %A0,%x2,%x3"
+{
+ return TARGET_DENSE_MATH ? "dm<apv> %A0,%x2,%x3" : "<apv> %A0,%x2,%x3";
+}
[(set_attr "type" "mma")])
-(define_insn "mma_<vvi4i4i8>"
+(define_insn "mma_pm<vvi4i4i8>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -621,11 +632,15 @@
(match_operand:SI 5 "u8bit_cint_operand" "n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
- "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
+ : "pm<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<avvi4i4i8>"
+(define_insn "mma_pm<avvi4i4i8>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -635,11 +650,15 @@
(match_operand:SI 6 "u8bit_cint_operand" "n,n")]
MMA_AVVI4I4I8))]
"TARGET_MMA"
- "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
+ : "pm<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<vvi4i4i2>"
+(define_insn "mma_pm<vvi4i4i2>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -648,11 +667,15 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
- "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
+ : "pm<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<avvi4i4i2>"
+(define_insn "mma_pm<avvi4i4i2>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -662,11 +685,15 @@
(match_operand:SI 6 "const_0_to_3_operand" "n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
- "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
+ : "pm<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<vvi4i4>"
+(define_insn "mma_pm<vvi4i4>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -674,11 +701,15 @@
(match_operand:SI 4 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
- "<vvi4i4> %A0,%x1,%x2,%3,%4"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<vvi4i4> %A0,%x1,%x2,%3,%4"
+ : "pm<vvi4i4> %A0,%x1,%x2,%3,%4");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<avvi4i4>"
+(define_insn "mma_pm<avvi4i4>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -687,11 +718,15 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
- "<avvi4i4> %A0,%x2,%x3,%4,%5"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<avvi4i4> %A0,%x2,%x3,%4,%5"
+ : "pm<avvi4i4> %A0,%x2,%x3,%4,%5");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<pvi4i2>"
+(define_insn "mma_pm<pvi4i2>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -699,11 +734,15 @@
(match_operand:SI 4 "const_0_to_3_operand" "n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
- "<pvi4i2> %A0,%x1,%x2,%3,%4"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<pvi4i2> %A0,%x1,%x2,%3,%4"
+ : "pm<pvi4i2> %A0,%x1,%x2,%3,%4");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<apvi4i2>"
+(define_insn "mma_pm<apvi4i2>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
@@ -712,11 +751,15 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
- "<apvi4i2> %A0,%x2,%x3,%4,%5"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<apvi4i2> %A0,%x2,%x3,%4,%5"
+ : "pm<apvi4i2> %A0,%x2,%x3,%4,%5");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<vvi4i4i4>"
+(define_insn "mma_pm<vvi4i4i4>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -725,11 +768,15 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
- "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
+ : "pm<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
-(define_insn "mma_<avvi4i4i4>"
+(define_insn "mma_pm<avvi4i4i4>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
@@ -739,6 +786,10 @@
(match_operand:SI 6 "const_0_to_15_operand" "n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
- "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
+{
+ return (TARGET_DENSE_MATH
+ ? "pmdm<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
+ : "pm<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6");
+}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
