[gcc r15-5551] rs6000: Add veqv support to *eqv3_internal1

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:2441dc2495d257c4894a4d0c8d36cfbdc851579c

commit r15-5551-g2441dc2495d257c4894a4d0c8d36cfbdc851579c
Author: Kewen Lin <li...@linux.ibm.com>
Date:   Thu Nov 21 07:41:33 2024 +0000

    rs6000: Add veqv support to *eqv<mode>3_internal1
    
    When making patch to replace TARGET_P8_VECTOR, I noticed
    for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
    operations, we only exploited the vsx version.  I think it
    is an oversight, this patch is to consider veqv as well.
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
            insn veqv if TARGET_ALTIVEC and operands are 
altivec_register_operand.

Diff:
---
 gcc/config/rs6000/rs6000.md | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2598059280bf..ca91a24795b1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7557,9 +7557,12 @@
          (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
   "TARGET_P8_VECTOR"
 {
-  if (vsx_register_operand (operands[0], <MODE>mode))
+  if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
     return "xxleqv %x0,%x1,%x2";
 
+  if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
+    return "veqv %0,%1,%2";
+
   return "#";
 }
   "TARGET_P8_VECTOR && reload_completed