https://gcc.gnu.org/g:164fbe01d59a56ab6eb381345fa1555263c854fa
commit r15-5506-g164fbe01d59a56ab6eb381345fa1555263c854fa
Author: Richard Sandiford <richard.sandif...@arm.com>
Date: Wed Nov 20 13:27:40 2024 +0000
aarch64: Fix the choice of unspec in two SME patterns
@aarch64_sme_write<mode> and *aarch64_sme_write<mode>_plus
were using UNSPEC_SME_READ instead of UNSPEC_SME_WRITE.
gcc/
* config/aarch64/aarch64-sme.md (@aarch64_sme_write<mode>)
(*aarch64_sme_write<mode>_plus): Use UNSPEC_SME_WRITE instead
of UNSPEC_SME_READ.
Diff:
---
gcc/config/aarch64/aarch64-sme.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sme.md
b/gcc/config/aarch64/aarch64-sme.md
index 525ded44c99f..e8a24e0b2f6f 100644
--- a/gcc/config/aarch64/aarch64-sme.md
+++ b/gcc/config/aarch64/aarch64-sme.md
@@ -848,7 +848,7 @@
(reg:DI SME_STATE_REGNUM)
(match_operand:SI 0 "register_operand" "Uci")
(match_operand:SVE_DIx24 1 "aligned_register_operand"
"Uw<vector_count>")]
- UNSPEC_SME_READ))]
+ UNSPEC_SME_WRITE))]
"TARGET_STREAMING_SME2"
"mova\tza.d[%w0, 0, vgx<vector_count>], %1"
)
@@ -861,7 +861,7 @@
(plus:SI (match_operand:SI 0 "register_operand" "Uci")
(match_operand:SI 1 "const_0_to_7_operand"))
(match_operand:SVE_DIx24 2 "aligned_register_operand"
"Uw<vector_count>")]
- UNSPEC_SME_READ))]
+ UNSPEC_SME_WRITE))]
"TARGET_STREAMING_SME2"
"mova\tza.d[%w0, %1, vgx<vector_count>], %2"
)
