[gcc r15-3578] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:6bd3ee7f2f2f4beed5b9d9a530736ad69d2cac42

commit r15-3578-g6bd3ee7f2f2f4beed5b9d9a530736ad69d2cac42
Author: Pan Li <pan2...@intel.com>
Date:   Wed Sep 11 07:00:13 2024 +0800

    RISC-V: Fix asm check for Vector SAT_* due to middle-end change
    
    The middle-end change makes the effect on the layout of the assembly
    for vector SAT_*.  This patch would like to fix it and make it robust.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust
            asm check and make it robust.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
    
    Signed-off-by: Pan Li <pan2...@intel.com>

Diff:
---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c        | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c         | 4 +---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c         | 5 ++---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c   | 5 +++--
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c   | 5 +++--
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c   | 5 +++--
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c       | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c       | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c       | 9 ++++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c       | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c        | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c       | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c       | 9 ++++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c       | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c       | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c        | 9 ++++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c        | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c        | 5 ++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c        | 7 ++++---
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c        | 9 ++++++---
 99 files changed, 179 insertions(+), 294 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
index 348313b511f4..d7d1dae010d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
index 425d4c768d6a..4397c10943a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
index 903ae36e464f..b93b582680f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
index b9db496f2fa8..ec3c6af4ee65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 72d17c0a971e..35f17c1b82d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
index 1aa4fbe701fc..116908431604 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 664fa61d67c7..9949047a6c7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
index f752327e9517..84c44f9a46bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
index 352e22e56e5c..5f61acbec0d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
index 7a1996d38bc7..eb4486ca765b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
index c01c9f468a4a..470eb6b3cfec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
index e4f7c64331b4..b381c05091ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
index 66ca4cd2749f..6bd2c30c1397 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
index 2e77b067cf37..c525ba97c529 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index 2e824049874b..41372d08e52d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
index 9283ce340b86..dddebb54426f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
index fcf7c9281400..ad5162d10a03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
index a5ca9228a20f..39c20b3cea64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
index 9d379ae46a12..6eefaeebf318 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
index 7b89fe1c3cfb..78beb1bd39e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
index f7c37df28885..369fa296d08f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index fbf57ff16421..e827cdd16570 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
index a0847c90f3f5..97a9b1fb9732 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
index e8b6de3ceb38..af16f48e228a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
index 57f4bf2c4275..0a8eabfbad1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
index 47a3bc1c2f28..38cbdfbcf075 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
index 3556761c430b..8da2cb413d80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
index c89ecea75cc6..fe8a5a8262d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
index 0f0f4542fb2e..1aeb24eed0d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
index e0e311d8b5b9..0d2b0e4ab809 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
index b76b231c06ee..168c269f75e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
index b13ff0aad8b0..d636302842cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index f0ce17d19591..5d2143017273 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index fac941945e9e..e50121bd0319 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index 0c6afc391b41..de460c176a2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index 41fe3b86deb1..96e06f0c6be2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index a52e38a7ed28..dffe957629a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 1ee8391d8838..97b2e17e74aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index d74a98224318..978c37ca1384 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index 70284382fba0..f43c5711ecaf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index d44514cdb974..f435b6e08311 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 5dbbf202b1f3..74fe1e31804e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index 4696753b903c..b83b87b2b1bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index c73413a4597a..549970684fab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index b963ba1e1e1c..0ae3c37a7834 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index fc2682bd24f2..e16a0d22cbbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 4e51e4aa7f82..6b4bc69c005d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index b16925ebac36..6be7c7669dea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index 9d99a4ea71cd..e9eb157fb9d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 424551e15006..4980789dcd48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index 110318824d86..2a4d1cc93e7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 981c0713c18c..8c14d9a2c01e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 159153727132..32d3a62d3038 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 9c971f6a3d1e..8c098ac336a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 447b6814b8ab..2af04851e04a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index 09bcd0d34689..4a4fc7463266 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index 704f560b79ad..5c912a32549b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 8011f6c19ccf..50aa0ae59d7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 2a5727677edd..329dd230b02f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index 4a7d7e55c9f4..a024eadc2a75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index cfad5d787e37..56216e976206 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 721fd27a2889..707bfd2e1c69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index 1e3b5e7bf3e9..e7dc212fe520 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index 4bc3205dc308..b814830da32b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index 3ec28cd3fc74..e6c6aaac800d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 5eca3debeaf2..21727fb3a43e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 656c35cc22a1..716e58e8ae39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index 942d2e91acc1..e1d78aff28c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index c27fc4d53312..9911cbcfb378 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 817435955a5f..8c83af1fc674 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index 42cf16f13b06..d76d754b7218 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index 9eb26d9f52c5..3b6b53274f2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index ab2287032d6b..792d8a028772 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 2c752e722586..67780360ce1e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 7f89d7099b07..04f2d0b2d95c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index ae3e44cd57e8..60ab5382fa9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
index f5084e503ebd..2566450445f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index e2ab880a1aca..f90432bb9031 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index e996c9442dd7..5330e19c6792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
index 49bdbdc36062..45d74eab2cdb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
index 3ff696edcfee..c9ce87882745 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
index 7fca4a43fd30..5529c710f921 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
index 201fcaa4f694..6d773e96da39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
index 99a9600102c6..808f62bff10f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
index f1bd5400f6b4..12a0e2ff3801 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
index a80cefe46ab0..9c7979d326cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
index 2516468fd167..cf6f404f65ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
index 9a4d261d052d..2e497b7ec1c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
index 5f0b71be8349..dd996d21c5ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
index 059758b8bb3d..a6c125408ce9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
index 6e094d071119..2551b2f5a057 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
index 707b20b0e01a..bfcfa805e19e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
index 5df05f72cbb5..787c5644bb08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
index 89dd65374a55..b236c2a2caf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
index 851a20e5037b..1747585c59e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
index 8ae3bc243cd3..fd30184b1de4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
index a5b566b6d80e..dc9bbb5fe96d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
index a6df321057ee..0525b8f5159b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
index 7c68825213f4..96621231999f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)