https://gcc.gnu.org/g:4257b13aa62b5307dceaa686ac15088f367fa608
commit 4257b13aa62b5307dceaa686ac15088f367fa608
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Sep 3 22:20:30 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 93 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index d650b6ef609d..0826011aaae0 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,98 @@
+==================== Branch work177-bugs, patch #201 ====================
+
+Optimize splat of a V2DF/V2DI extract with constant element
+
+We had optimizations for splat of a vector extract for the other vector
+types, but we missed having one for V2DI and V2DF. This patch adds a
+combiner insn to do this optimization.
+
+In looking at the source, we had similar optimizations for V4SI and V4SF
+extract and splats, but we missed doing V2DI/V2DF.
+
+Without the patch for the code:
+
+ vector long long splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+the compiler generates (on a little endian power9):
+
+ splat_dup_l_0:
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+Now it generates:
+
+ splat_dup_l_0:
+ xxpermdi 34,34,34,3
+ blr
+
+2024-08-19 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/builtins-1.c: Adjust insn count.
+ * gcc.target/powerpc/pr99293.c: New test.
+
+==================== Branch work177-bugs, patch #200 ====================
+
+Add better support for shifting vectors with 64-bit elements
+
+This patch fixes PR target/89213 to allow better code to be generated to do
+constant shifts of V2DI/V2DF vectors. Previously GCC would do constant shifts
+of vectors with 64-bit elements by using:
+
+ XXSPLTIB 32,4
+ VEXTSB2D 0,0
+ VSRAD 2,2,0
+
+I.e., the PowerPC does not have a VSPLTISD instruction to load -15..14 for the
+64-bit shift count in one instruction. Instead, it would need to load a byte
+and then convert it to 64-bit.
+
+With this patch, GCC now realizes that the vector shift instructions will look
+at the bottom 6 bits for the shift count, and it can use either a VSPLTISW or
+XXSPLTIB instruction to load the shift count.
+
+2024-08-19 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/89213
+ * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec.
+ (VSHIFT_MODE): New mode iterator.
+ (vshift_code): New code iterator.
+ (vshift_attr): New code attribute.
+ (altivec_<mode>_<vshift_attr>_const): New pattern to optimize
+ vector long long/int shifts by a constant.
+ (altivec_<mode>_shift_const): New helper insn to load up a
+ constant used by the shift operation.
+ * config/rs6000/predicates.md (vector_shift_constant): New
+ predicate.
+
+gcc/testsuite/
+
+ PR target/89213
+ * gcc.target/powerpc/pr89213.c: New test.
+ * gcc.target/powerpc/vec-rlmi-rlnm.c: Update instruction count.
+
==================== Branch work177-bugs, baseline ====================
+Add ChangeLog.bugs and update REVISION.
+
+2024-08-16 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.bugs: New file for branch.
+ * REVISION: Update.
+
2024-09-03 Michael Meissner <meiss...@linux.ibm.com>
Clone branch
-
