https://gcc.gnu.org/g:d8bc31d973d2ab3fabb5e85e7c4354ffb2283512
commit r15-3437-gd8bc31d973d2ab3fabb5e85e7c4354ffb2283512
Author: Andrew Pinski <quic_apin...@quicinc.com>
Date: Tue Sep 3 17:10:37 2024 -0700
aarch64: Fix testcase vec-init-22-speed.c [PR116589]
For this testcase, the trunk produces:
```
f_s16:
fmov s31, w0
fmov s0, w1
```
While the testcase was expecting what was produced in GCC 14:
```
f_s16:
sxth w0, w0
sxth w1, w1
fmov d31, x0
fmov d0, x1
```
After r15-1575-gea8061f46a30 the code was:
```
dup v31.4h, w0
dup v0.4h, w1
```
But when ext-dce was added with r15-1901-g98914f9eba5f19, we get the better
code generation now and only fmov's.
Pushed as obvious after running the testcase.
PR target/116589
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vec-init-22-speed.c: Update scan for better
code gen.
Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>
Diff:
---
gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c
b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c
index 993ef8c41613..6edc82831a00 100644
--- a/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c
+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c
@@ -7,6 +7,6 @@
#include "vec-init-22.h"
-/* { dg-final { scan-assembler-times {\tfmov\td[0-9]+, x[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {\tfmov\ts[0-9]+, w[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {\tins\tv[0-9]+\.h\[[1-3]\], w[0-9]+} 6 }
} */
/* { dg-final { scan-assembler {\tzip1\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h}
} } */
