[gcc r15-3013] aarch64: Implement 16-byte vector mode const0 store by TImode

[HaoChen Gui via Gcc-cvs]

https://gcc.gnu.org/g:8d6c6fbc5271dde433998c09407b30e2cf195420

commit r15-3013-g8d6c6fbc5271dde433998c09407b30e2cf195420
Author: Haochen Gui <guih...@gcc.gnu.org>
Date:   Mon Aug 19 10:35:47 2024 +0800

    aarch64: Implement 16-byte vector mode const0 store by TImode
    
    gcc/
            * config/aarch64/aarch64-simd.md (mov<mode> for VSTRUCT_QD):
            Expand 16-byte vector mode const0 store by TImode.

Diff:
---
 gcc/config/aarch64/aarch64-simd.md | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index 475f19766c3..23c03a96371 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7809,7 +7809,16 @@
        (match_operand:VSTRUCT_QD 1 "general_operand"))]
   "TARGET_FLOAT"
 {
-  if (can_create_pseudo_p ())
+  if (known_eq (GET_MODE_SIZE (<MODE>mode), 16)
+      && operands[1] == CONST0_RTX (<MODE>mode)
+      && MEM_P (operands[0])
+      && (can_create_pseudo_p ()
+         || memory_address_p (TImode, XEXP (operands[0], 0))))
+    {
+      operands[0] = adjust_address (operands[0], TImode, 0);
+      operands[1] = CONST0_RTX (TImode);
+    }
+  else if (can_create_pseudo_p ())
     {
       if (GET_CODE (operands[0]) != REG)
        operands[1] = force_reg (<MODE>mode, operands[1]);