[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix testcase missing arch attribute

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:bdb2115f7ee854a6daecf6079274700321f1a2b5

commit bdb2115f7ee854a6daecf6079274700321f1a2b5
Author: Edwin Lu <e...@rivosinc.com>
Date:   Tue Jul 16 17:43:45 2024 -0700

    RISC-V: Fix testcase missing arch attribute
    
    The C + F extention implies the zcf extension on rv32. Add missing zcf
    extension for the rv32 target.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/target-attr-16.c: Update expected assembly
    
    Signed-off-by: Edwin Lu <e...@rivosinc.com>
    (cherry picked from commit 5bb01e91d40c34e8f8230b142f7ebff3d6aa88d1)

Diff:
---
 gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c 
b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
index 1c7badccdeee..c6b626d0c6ce 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
@@ -24,5 +24,5 @@ void bar (void)
 {
 }
 
-/* { dg-final { scan-assembler-times ".option arch, 
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
 4 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times ".option arch, 
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0"
 4 { target { rv32 } } } } */
 /* { dg-final { scan-assembler-times ".option arch, 
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
 4 { target { rv64 } } } } */