https://gcc.gnu.org/g:5021a6c04765ed9f06013827155f7c65b9d785fe
commit 5021a6c04765ed9f06013827155f7c65b9d785fe
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jul 23 10:11:54 2024 -0400
Move architecture flags from isa flags
2024-07-22 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add
support for separating the architecture flags from the ISA flags.
(rs6000_cpu_cpp_builtins): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros):
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture flags instead of isa flags.
(rs6000_clone_map): Likewise.
(rs6000_target_modify_macros_ptr): Update declaration.
(get_arch_flags): New function.
(rs6000_debug_reg_global): Add support for separating architecture
flags from the ISA flags.
(rs6000_print_isa_options):Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): Likewise.
(rs6000_pragma_target_parse): Likewise.
(rs6000_function_specific_save): Likewise.
(rs6000_function_specific_restore): Likewise.
(rs6000_function_specific_print): Likewise.
(rs6000_print_options_internal): Likewise.
(rs6000_print_isa_options): Likewise.
(rs6000_clone_priority): Switch to using architecture flags.
(rs6000_can_inline_p): Check if the arch flags match along with the
isa
flags.
* config/rs6000/rs6000.h (enum arch_bits): New enumeration.
(ARCH_MASK_*): New architecture masks for a specific processor.
(ARCH_FLAGS_*): New architecture masks for all of the architecture
masks
set for a specific processor.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New target save area.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 23 ++---
gcc/config/rs6000/rs6000-protos.h | 5 +-
gcc/config/rs6000/rs6000.cc | 188 +++++++++++++++++++++++++++++---------
gcc/config/rs6000/rs6000.h | 36 ++++++++
gcc/config/rs6000/rs6000.opt | 8 ++
5 files changed, 205 insertions(+), 55 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 68519e1397f1..2ffaee165885 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char
*name)
#pragma GCC target, we need to adjust the macros dynamically. */
void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+ HOST_WIDE_INT arch_flags)
{
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
summary of the flags associated with particular cpu
definitions. */
- /* rs6000_isa_flags based options. */
+ /* rs6000_isa_flags and rs6000_arch_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -421,21 +422,21 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
if ((flags & OPTION_MASK_MFCRF) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((flags & OPTION_MASK_POPCNTB) != 0)
+ if ((arch_flags & ARCH_MASK_POWER4) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((flags & OPTION_MASK_FPRND) != 0)
+ if ((arch_flags & ARCH_MASK_POWER5) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((flags & OPTION_MASK_CMPB) != 0)
+ if ((arch_flags & ARCH_MASK_POWER6) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & OPTION_MASK_POPCNTD) != 0)
+ if ((arch_flags & ARCH_MASK_POWER7) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
- if ((flags & OPTION_MASK_POWER8) != 0)
+ if ((arch_flags & ARCH_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
- if ((flags & OPTION_MASK_MODULO) != 0)
+ if ((arch_flags & ARCH_MASK_POWER9) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
- if ((flags & OPTION_MASK_POWER10) != 0)
+ if ((arch_flags & ARCH_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
- if ((flags & OPTION_MASK_POWER11) != 0)
+ if ((arch_flags & ARCH_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -605,7 +606,7 @@ void
rs6000_cpu_cpp_builtins (cpp_reader *pfile)
{
/* Define all of the common macros. */
- rs6000_target_modify_macros (true, rs6000_isa_flags);
+ rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags);
if (TARGET_FRE)
builtin_define ("__RECIP__");
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index b40557a85577..da658cd5ab2e 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -323,8 +323,9 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
extern bool rs6000_pragma_target_parse (tree, tree);
#endif
extern void rs6000_activate_target_options (tree new_tree);
-extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT);
-extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
+extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
+extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
+ HOST_WIDE_INT);
#ifdef NO_DOLLAR_IN_LABEL
const char * rs6000_xcoff_strip_dollar (const char *);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index eddd2adbab59..381d439c0cf3 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
/* Map compiler ISA bits into HWCAP names. */
struct clone_map {
- HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
+ HOST_WIDE_INT arch_mask; /* rs6000_arch_mask. */
const char *name; /* name to use in __builtin_cpu_supports. */
};
static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
- { 0, "" }, /* Default options. */
- { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
- { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
- { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
- { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
- { OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
+ { 0, "" }, /* Default options. */
+ { ARCH_MASK_POWER6, "arch_2_05" }, /* ISA 2.05 (power6). */
+ { ARCH_MASK_POWER7, "arch_2_06" }, /* ISA 2.06 (power7). */
+ { ARCH_MASK_POWER8, "arch_2_07" }, /* ISA 2.07 (power8). */
+ { ARCH_MASK_POWER9, "arch_3_00" }, /* ISA 3.0 (power9). */
+ { ARCH_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
};
@@ -277,7 +277,7 @@ bool cpu_builtin_p = false;
/* Pointer to function (in rs6000-c.cc) that can define or undefine target
macros that have changed. Languages that don't support the preprocessor
don't link in rs6000-c.cc, so we can't call it directly. */
-void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
+void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
/* Simplfy register classes into simpler classifications. We assume
GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
@@ -1170,7 +1170,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class)
const int INSN_NOT_AVAILABLE = -1;
static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT);
+ HOST_WIDE_INT, HOST_WIDE_INT);
static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
@@ -1817,6 +1817,36 @@ rs6000_cpu_name_lookup (const char *name)
return -1;
}
+
+/* Map the processor into the arch bits that are set off of -mcpu=<xxx> instead
+ of having an internal -m<foo> option. */
+
+static HOST_WIDE_INT
+get_arch_flags (int cpu_index)
+{
+ if (cpu_index < 0)
+ return 0;
+
+ enum processor_type processor = processor_target_table[cpu_index].processor;
+
+ switch (processor)
+ {
+ case PROCESSOR_POWER4: return ARCH_FLAGS_POWER4;
+ case PROCESSOR_POWER5: return ARCH_FLAGS_POWER5;
+ case PROCESSOR_POWER6: return ARCH_FLAGS_POWER6;
+ case PROCESSOR_POWER7: return ARCH_FLAGS_POWER7;
+ case PROCESSOR_POWER8: return ARCH_FLAGS_POWER8;
+ case PROCESSOR_POWER9: return ARCH_FLAGS_POWER9;
+ case PROCESSOR_POWER10: return ARCH_FLAGS_POWER10;
+ case PROCESSOR_POWER11: return ARCH_FLAGS_POWER11;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@@ -2398,9 +2428,10 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_cpu_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_cpu_index].target_enable;
+ HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_cpu_index);
sprintf (flags_buffer, "-mcpu=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
@@ -2410,21 +2441,26 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_tune_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_tune_index].target_enable;
+ HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_tune_index);
sprintf (flags_buffer, "-mtune=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
cl_target_option_save (&cl_opts, &global_options, &global_options_set);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
- rs6000_isa_flags);
+ rs6000_isa_flags, 0);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
- rs6000_isa_flags_explicit);
+ rs6000_isa_flags_explicit, 0);
+
+ if (rs6000_arch_flags)
+ rs6000_print_isa_options (stderr, 0, "rs6000_arch_flags", 0,
+ rs6000_arch_flags);
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
@@ -3625,7 +3661,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Print defaults. */
if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
/* Remember the explicit arguments. */
if (global_init_p)
@@ -3756,6 +3792,8 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
}
+ rs6000_arch_flags = get_arch_flags (cpu_index);
+
/* Don't expect powerpc64 enabled on those OSes with OS_MISSING_POWERPC64,
since they do not save and restore the high half of the GPRs correctly
in all cases. If the user explicitly specifies it, we won't interfere
@@ -3823,8 +3861,7 @@ rs6000_option_override_internal (bool global_init_p)
/* If little-endian, default to -mstrict-align on older processors. */
if (!BYTES_BIG_ENDIAN
- && !(processor_target_table[tune_index].target_enable
- & OPTION_MASK_POWER8))
+ && (get_arch_flags (tune_index) & ARCH_MASK_POWER8) == 0)
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
/* Add some warnings for VSX. */
@@ -3870,7 +3907,8 @@ rs6000_option_override_internal (bool global_init_p)
& ~rs6000_isa_flags_explicit);
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags,
+ rs6000_arch_flags);
#ifdef XCOFF_DEBUGGING_INFO
/* For AIX default to 64-bit DWARF. */
@@ -4232,7 +4270,8 @@ rs6000_option_override_internal (bool global_init_p)
/* Print the options after updating the defaults. */
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags,
+ rs6000_arch_flags);
/* E500mc does "better" if we inline more aggressively. Respect the
user's opinion, though. */
@@ -4339,7 +4378,8 @@ rs6000_option_override_internal (bool global_init_p)
TARGET_NO_FP_IN_TOC = 1;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags,
+ rs6000_arch_flags);
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
@@ -4406,7 +4446,8 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags,
+ rs6000_arch_flags);
rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
&& rs6000_tune != PROCESSOR_POWER5
@@ -5897,27 +5938,28 @@ rs6000_machine_from_flags (void)
return "ppc64";
#endif
+ HOST_WIDE_INT arch_flags = rs6000_arch_flags;
HOST_WIDE_INT flags = rs6000_isa_flags;
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
| OPTION_MASK_ALTIVEC);
- if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER11) != 0)
return "power11";
- if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER10) != 0)
return "power10";
- if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER9) != 0)
return "power9";
- if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER8) != 0)
return "power8";
- if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER7) != 0)
return "power7";
- if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER6) != 0)
return "power6";
- if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+ if ((arch_flags & ARCH_MASK_POWER5) != 0)
return "power5";
- if ((flags & ISA_2_1_MASKS) != 0)
+ if ((arch_flags & ARCH_MASK_POWER4) != 0)
return "power4";
if ((flags & OPTION_MASK_POWERPC64) != 0)
return "ppc64";
@@ -24542,6 +24584,25 @@ static struct rs6000_opt_mask const rs6000_opt_masks[]
=
{ "string", 0, false, false },
};
+/* Similar structure for the arch bits that are set via -mcpu=<xxx> and not via
+ a separate -m<yyy> option. */
+struct rs6000_arch_mask {
+ const char *name; /* option name */
+ const HOST_WIDE_INT mask; /* mask to set */
+};
+
+static struct rs6000_arch_mask const rs6000_arch_masks[] =
+{
+ { "power4", ARCH_MASK_POWER4 },
+ { "power5", ARCH_MASK_POWER5 },
+ { "power6", ARCH_MASK_POWER6 },
+ { "power7", ARCH_MASK_POWER7 },
+ { "power8", ARCH_MASK_POWER8 },
+ { "power9", ARCH_MASK_POWER9 },
+ { "power10", ARCH_MASK_POWER10 },
+ { "power11", ARCH_MASK_POWER11 },
+};
+
/* Option variables that we want to support inside attribute((target)) and
#pragma GCC target operations. */
@@ -24896,6 +24957,7 @@ rs6000_pragma_target_parse (tree args, tree pop_target)
tree cur_tree;
struct cl_target_option *prev_opt, *cur_opt;
HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
+ HOST_WIDE_INT prev_arch, cur_arch, diff_arch;
if (TARGET_DEBUG_TARGET)
{
@@ -24948,21 +25010,26 @@ rs6000_pragma_target_parse (tree args, tree
pop_target)
{
prev_opt = TREE_TARGET_OPTION (prev_tree);
prev_flags = prev_opt->x_rs6000_isa_flags;
+ prev_arch = prev_opt->x_rs6000_arch_flags;
cur_opt = TREE_TARGET_OPTION (cur_tree);
cur_flags = cur_opt->x_rs6000_isa_flags;
+ cur_arch = cur_opt->x_rs6000_arch_flags;
diff_flags = (prev_flags ^ cur_flags);
+ diff_arch = (prev_arch ^ cur_arch);
- if (diff_flags != 0)
+ if (diff_flags != 0 || diff_arch != 0)
{
/* Delete old macros. */
rs6000_target_modify_macros_ptr (false,
- prev_flags & diff_flags);
+ prev_flags & diff_flags,
+ prev_arch & diff_arch);
/* Define new macros. */
rs6000_target_modify_macros_ptr (true,
- cur_flags & diff_flags);
+ cur_flags & diff_flags,
+ cur_arch & diff_arch);
}
}
@@ -25076,6 +25143,7 @@ rs6000_function_specific_save (struct cl_target_option
*ptr,
{
ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
+ ptr->x_rs6000_arch_flags = opts->x_rs6000_arch_flags;
}
/* Restore the current options */
@@ -25088,6 +25156,7 @@ rs6000_function_specific_restore (struct gcc_options
*opts,
{
opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
+ opts->x_rs6000_arch_flags = ptr->x_rs6000_arch_flags;
(void) rs6000_option_override_internal (false);
}
@@ -25098,10 +25167,12 @@ rs6000_function_specific_print (FILE *file, int
indent,
struct cl_target_option *ptr)
{
rs6000_print_isa_options (file, indent, "Isa options set",
- ptr->x_rs6000_isa_flags);
+ ptr->x_rs6000_isa_flags,
+ ptr->x_rs6000_arch_flags);
rs6000_print_isa_options (file, indent, "Isa options explicit",
- ptr->x_rs6000_isa_flags_explicit);
+ ptr->x_rs6000_isa_flags_explicit,
+ ptr->x_rs6000_arch_flags);
}
/* Helper function to print the current isa or misc options on a line. */
@@ -25113,13 +25184,18 @@ rs6000_print_options_internal (FILE *file,
HOST_WIDE_INT flags,
const char *prefix,
const struct rs6000_opt_mask *opts,
- size_t num_elements)
+ size_t num_elements,
+ HOST_WIDE_INT arch_flags,
+ const char *arch_prefix,
+ const struct rs6000_arch_mask *arch_masks,
+ size_t num_arch)
{
size_t i;
size_t start_column = 0;
size_t cur_column;
size_t max_column = 120;
size_t prefix_len = strlen (prefix);
+ size_t arch_prefix_len = strlen (arch_prefix);
size_t comma_len = 0;
const char *comma = "";
@@ -25179,6 +25255,29 @@ rs6000_print_options_internal (FILE *file,
comma_len = strlen (", ");
}
+ /* Put out the architecture flag bits that are set via -mcpu=<xxx> and that
+ don't have a -m option. */
+ for (i = 0; i < num_arch; i++)
+ {
+ if ((arch_flags & arch_masks[i].mask) != 0)
+ {
+ const char *name = arch_masks[i].name;
+ size_t len = comma_len + arch_prefix_len + strlen (name);
+
+ cur_column += len;
+ if (cur_column > max_column)
+ {
+ fprintf (stderr, ", \\\n%*s", (int)start_column, "");
+ cur_column = start_column + len;
+ comma = "";
+ }
+
+ fprintf (file, "%s%s%s", comma, arch_prefix, name);
+ comma = ", ";
+ comma_len = strlen (", ");
+ }
+ }
+
fputs ("\n", file);
}
@@ -25186,11 +25285,13 @@ rs6000_print_options_internal (FILE *file,
static void
rs6000_print_isa_options (FILE *file, int indent, const char *string,
- HOST_WIDE_INT flags)
+ HOST_WIDE_INT flags, HOST_WIDE_INT arch_flags)
{
rs6000_print_options_internal (file, indent, string, flags, "-m",
&rs6000_opt_masks[0],
- ARRAY_SIZE (rs6000_opt_masks));
+ ARRAY_SIZE (rs6000_opt_masks),
+ arch_flags, "arch=", &rs6000_arch_masks[0],
+ ARRAY_SIZE (rs6000_arch_masks));
}
/* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
@@ -25280,7 +25381,7 @@ static int
rs6000_clone_priority (tree fndecl)
{
tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
- HOST_WIDE_INT isa_masks;
+ HOST_WIDE_INT arch_masks;
int ret = CLONE_DEFAULT;
tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
const char *attrs_str = NULL;
@@ -25296,12 +25397,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
- isa_masks = rs6000_isa_flags;
+ arch_masks = rs6000_arch_flags;
else
- isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+ arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
for (ret = CLONE_MAX - 1; ret != 0; ret--)
- if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+ if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
break;
}
@@ -25781,6 +25882,8 @@ rs6000_can_inline_p (tree caller, tree callee)
HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags;
HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags;
HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit;
+ HOST_WIDE_INT callee_arch = callee_opts->x_rs6000_arch_flags;
+ HOST_WIDE_INT caller_arch = caller_opts->x_rs6000_arch_flags;
cgraph_node *callee_node = cgraph_node::get (callee);
if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL)
@@ -25804,7 +25907,8 @@ rs6000_can_inline_p (tree caller, tree callee)
callee has explicitly enabled or disabled, then we must enforce that
the callee's and caller's options match exactly; see PR70010. */
if (((caller_isa & callee_isa) == callee_isa)
- && (caller_isa & explicit_isa) == (callee_isa & explicit_isa))
+ && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)
+ && (caller_arch & callee_arch) == callee_arch)
ret = true;
if (TARGET_DEBUG_TARGET)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 703be908d944..2053de1fc176 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2481,3 +2481,39 @@ while (0)
issues have been resolved. */
#define RS6000_DISABLE_SCALAR_MODULO 1
+
+/* List of architecture masks (to set the _ARCH_PWR<x> flag that don't have a
+ separate -m option. It the past, we would have -mpower11, -mpower10,
+ -mpower9, etc. but bad things would happen if the user did -mpower10 instead
+ of -mcpu=power10. Over time, older options will be removed as -m<option>
+ and moved into this list. */
+
+enum arch_bits {
+ ARCH_ENUM_POWER4 = 1,
+ ARCH_ENUM_POWER5,
+ ARCH_ENUM_POWER6,
+ ARCH_ENUM_POWER7,
+ ARCH_ENUM_POWER8,
+ ARCH_ENUM_POWER9,
+ ARCH_ENUM_POWER10,
+ ARCH_ENUM_POWER11
+};
+
+#define ARCH_MASK_POWER4 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER4)
+#define ARCH_MASK_POWER5 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER5)
+#define ARCH_MASK_POWER6 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER6)
+#define ARCH_MASK_POWER7 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER7)
+#define ARCH_MASK_POWER8 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER8)
+#define ARCH_MASK_POWER9 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER9)
+#define ARCH_MASK_POWER10 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER10)
+#define ARCH_MASK_POWER11 (HOST_WIDE_INT_1 << ARCH_ENUM_POWER11)
+
+/* Flags to set the architecture bits for a given cpu. */
+#define ARCH_FLAGS_POWER4 ARCH_MASK_POWER4
+#define ARCH_FLAGS_POWER5 (ARCH_FLAGS_POWER4 | ARCH_MASK_POWER5)
+#define ARCH_FLAGS_POWER6 (ARCH_FLAGS_POWER5 | ARCH_MASK_POWER6)
+#define ARCH_FLAGS_POWER7 (ARCH_FLAGS_POWER6 | ARCH_MASK_POWER7)
+#define ARCH_FLAGS_POWER8 (ARCH_FLAGS_POWER7 | ARCH_MASK_POWER8)
+#define ARCH_FLAGS_POWER9 (ARCH_FLAGS_POWER8 | ARCH_MASK_POWER9)
+#define ARCH_FLAGS_POWER10 (ARCH_FLAGS_POWER9 | ARCH_MASK_POWER10)
+#define ARCH_FLAGS_POWER11 (ARCH_FLAGS_POWER10 | ARCH_MASK_POWER11)
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 94323bd1db26..73dfb63a81ce 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -36,6 +36,14 @@ HOST_WIDE_INT rs6000_isa_flags_explicit
TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit
+;; Arch bits that are set via -mcpu=<xxx> but don't have a user -m<processor>
+;; option
+Variable
+HOST_WIDE_INT rs6000_arch_flags = 0
+
+TargetSave
+HOST_WIDE_INT x_rs6000_arch_flags
+
;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603
