https://gcc.gnu.org/g:902edc4a23a2d0f8d1c48f7fe6118f968a36839d

commit 902edc4a23a2d0f8d1c48f7fe6118f968a36839d
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Thu Jun 13 14:14:18 2024 -0400

    Restrict modes that can got in SPRs.
    
    2024-06-13  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): 
Restrict
            the modes that can go in SPR registers.
            * config/rs6000/rs6000.md (movsf_hardfloat): Eliminate alternatives 
for
            moving floating point to/from SPRs.
            (movsd_hardfloat): Likewise.
            (mov<mode>_softfloat): Likewise.
            (mov<mode>_softfloat32): Likewise.
            (mov<mode>_hardfloat64): Likewise.
            (mov<mode>_softfloat64): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 18 ++++++++-
 gcc/config/rs6000/rs6000.md | 96 +++++++++++++++++----------------------------
 2 files changed, 53 insertions(+), 61 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e4..02be24b1a914 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
 {
   int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+  bool orig_complex_p = false;
 
   if (COMPLEX_MODE_P (mode))
-    mode = GET_MODE_INNER (mode);
+    {
+      mode = GET_MODE_INNER (mode);
+      orig_complex_p = true;
+    }
 
   /* Vector pair modes need even/odd VSX register pairs.  Only allow vector
      registers.  */
@@ -1935,6 +1939,18 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
   if (CA_REGNO_P (regno))
     return mode == Pmode || mode == SImode;
 
+  /* Do some consistancy checks for SPRs.  Don't allow complex modes.
+     VRSAVE/VSCR are always 32-bit SPRs.  Don't allow floating point modes in
+     the other SPRs.  Don't allow large modes that don't fit in a single
+     register. */
+  if (regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+      return (!orig_complex_p && mode == SImode);
+
+  if (regno == LR_REGNO || regno == CTR_REGNO)
+    return (!orig_complex_p
+           && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+           && !SCALAR_FLOAT_MODE_P (mode));
+
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))
     return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 44d38df56f12..273541f0bcba 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8203,17 +8203,17 @@
 ;;
 ;;     LWZ          LFS        LXSSP       LXSSPX     STFS       STXSSP
 ;;     STXSSPX      STW        XXLXOR      LI         FMR        XSCPSGNDP
-;;     MR           MT<x>      MF<x>       NOP        XXSPLTIDP
+;;     MR           XXSPLTIDP
 
 (define_insn "movsf_hardfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand"
         "=!r,       f,         v,          wa,        m,         wY,
          Z,         m,         wa,         !r,        f,         wa,
-         !r,        *c*l,      !r,         *h,        wa")
+         !r,        wa")
        (match_operand:SF 1 "input_operand"
         "m,         m,         wY,         Z,         f,         v,
          wa,        r,         j,          j,         f,         wa,
-         r,         r,         *h,         0,         eP"))]
+         r,         eP"))]
   "(register_operand (operands[0], SFmode)
    || register_operand (operands[1], SFmode))
    && TARGET_HARD_FLOAT
@@ -8233,32 +8233,29 @@
    fmr %0,%1
    xscpsgndp %x0,%x1,%x1
    mr %0,%1
-   mt%0 %1
-   mf%1 %0
-   nop
    #"
   [(set_attr "type"
        "load,       fpload,    fpload,     fpload,    fpstore,   fpstore,
         fpstore,    store,     veclogical, integer,   fpsimple,  fpsimple,
-        *,          mtjmpr,    mfjmpr,     *,         vecperm")
+        *,          vecperm")
    (set_attr "isa"
        "*,          *,         p9v,        p8v,       *,         p9v,
         p8v,        *,         *,          *,         *,         *,
-        *,          *,         *,          *,         p10")
+        *,          p10")
    (set_attr "prefixed"
        "*,          *,         *,          *,         *,         *,
         *,          *,         *,          *,         *,         *,
-        *,          *,         *,          *,         yes")])
+        *,          yes")])
 
 ;;     LWZ          LFIWZX     STW        STFIWX     MTVSRWZ    MFVSRWZ
-;;     FMR          MR         MT%0       MF%1       NOP
+;;     FMR          MR
 (define_insn "movsd_hardfloat"
   [(set (match_operand:SD 0 "nonimmediate_operand"
         "=!r,       d,         m,         ?Z,        ?d,        ?r,
-         f,         !r,        *c*l,      !r,        *h")
+         f,         !r")
        (match_operand:SD 1 "input_operand"
         "m,         ?Z,        r,         wx,        r,         d,
-         f,         r,         r,         *h,        0"))]
+         f,         r"))]
   "(register_operand (operands[0], SDmode)
    || register_operand (operands[1], SDmode))
    && TARGET_HARD_FLOAT"
@@ -8270,49 +8267,38 @@
    mtvsrwz %x0,%1
    mfvsrwz %0,%x1
    fmr %0,%1
-   mr %0,%1
-   mt%0 %1
-   mf%1 %0
-   nop"
+   mr %0,%1"
   [(set_attr "type"
        "load,       fpload,    store,     fpstore,   mtvsr,     mfvsr,
-        fpsimple,   *,         mtjmpr,    mfjmpr,    *")
+        fpsimple,   *")
    (set_attr "isa"
        "*,          p7,        *,         *,         p8v,       p8v,
-        *,          *,         *,         *,         *")])
+        *,          *")])
 
-;;     MR           MT%0       MF%0       LWZ        STW        LI
-;;     LIS          G-const.   F/n-const  NOP
+;;     MR     LWZ    STW        LI     LIS    G-const. F/n-const
 (define_insn "*mov<mode>_softfloat"
   [(set (match_operand:FMOVE32 0 "nonimmediate_operand"
-       "=r,         *c*l,      r,         r,         m,         r,
-          r,         r,         r,         *h")
+       "=r,   r,     m,         r,     r,     r,       r")
 
        (match_operand:FMOVE32 1 "input_operand"
-        "r,         r,         *h,        m,         r,         I,
-          L,         G,         Fn,        0"))]
+        "r,   m,     r,         I,     L,     G,       Fn"))]
 
   "(gpc_reg_operand (operands[0], <MODE>mode)
    || gpc_reg_operand (operands[1], <MODE>mode))
    && TARGET_SOFT_FLOAT"
   "@
    mr %0,%1
-   mt%0 %1
-   mf%1 %0
    lwz%U1%X1 %0,%1
    stw%U0%X0 %1,%0
    li %0,%1
    lis %0,%v1
    #
-   #
-   nop"
+   #"
   [(set_attr "type"
-       "*,          mtjmpr,    mfjmpr,    load,      store,     *,
-        *,          *,         *,         *")
+       "*,    load,  store,     *,     *,     *,       *")
 
    (set_attr "length"
-       "*,          *,         *,         *,         *,         *,
-         *,          *,         8,         *")])
+       "*,    *,     *,         *,     *,     *,       8")])
 
 ;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
 ;; (set (reg:SF ...) (subreg:SF (reg:SI ...) 0))
@@ -8592,20 +8578,20 @@
 
 ;;           STFD         LFD         FMR         LXSD        STXSD
 ;;           LXSDX        STXSDX      XXLOR       XXLXOR      LI 0
-;;           STD          LD          MR          MT{CTR,LR}  MF{CTR,LR}
-;;           NOP          MFVSRD      MTVSRD      XXSPLTIDP
+;;           STD          LD          MR          MFVSRD      MTVSRD
+;;           XXSPLTIDP
 
 (define_insn "*mov<mode>_hardfloat64"
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
            "=m,           d,          d,          <f64_p9>,   wY,
              <f64_av>,    Z,          <f64_vsx>,  <f64_vsx>,  !r,
-             YZ,          r,          !r,         *c*l,       !r,
-            *h,           r,          <f64_dm>,   wa")
+             YZ,          r,          !r,         r,          <f64_dm>,
+             wa")
        (match_operand:FMOVE64 1 "input_operand"
             "d,           m,          d,          wY,         <f64_p9>,
              Z,           <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
-             r,           YZ,         r,          r,          *h,
-             0,           <f64_dm>,   r,          eP"))]
+             r,           YZ,         r,          <f64_dm>,   r,
+             eP"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8623,40 +8609,34 @@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
    mr %0,%1
-   mt%0 %1
-   mf%1 %0
-   nop
    mfvsrd %0,%x1
    mtvsrd %x0,%1
    #"
   [(set_attr "type"
             "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
              fpload,      fpstore,    veclogical, veclogical, integer,
-             store,       load,       *,          mtjmpr,     mfjmpr,
-             *,           mfvsr,      mtvsr,      vecperm")
+             store,       load,       *,          mfvsr,      mtvsr,
+             vecperm")
    (set_attr "size" "64")
    (set_attr "isa"
             "*,           *,          *,          p9v,        p9v,
              p7v,         p7v,        *,          *,          *,
-             *,           *,          *,          *,          *,
-             *,           p8v,        p8v,        p10")
+             *,           *,          *,          p8v,        p8v,
+             p10")
    (set_attr "prefixed"
             "*,           *,          *,          *,          *,
              *,           *,          *,          *,          *,
              *,           *,          *,          *,          *,
-             *,           *,          *,          *")])
+             *")])
 
-;;           STD      LD       MR      MT<SPR> MF<SPR> G-const
-;;           H-const  F-const  Special
+;;           STD      LD       MR     G-const    H-const  F-const
 
 (define_insn "*mov<mode>_softfloat64"
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
-           "=Y,       r,      r,      *c*l,   r,      r,
-             r,       r,      *h")
+           "=Y,       r,      r,      r,        r,        r")
 
        (match_operand:FMOVE64 1 "input_operand"
-            "r,       Y,      r,      r,      *h,     G,
-             H,       F,      0"))]
+            "r,       Y,      r,      G,        H,        F"))]
 
   "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
@@ -8665,19 +8645,15 @@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
    mr %0,%1
-   mt%0 %1
-   mf%1 %0
-   #
    #
    #
-   nop"
+   #"
+;;           STD      LD       MR     G-const    H-const  F-const
   [(set_attr "type"
-            "store,   load,   *,      mtjmpr, mfjmpr, *,
-             *,       *,      *")
+            "store,   load,    *,     *,         *,       *")
 
    (set_attr "length"
-            "*,       *,      *,      *,      *,      8,
-             12,      16,     *")])
+            "*,       *,      *,      8,         12,      16")])
 
 ;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
 ;; constants that look like DFmode floating point values where both elements

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