https://gcc.gnu.org/g:70490d46340627347654fe28f885a8c8577583c1
commit 70490d46340627347654fe28f885a8c8577583c1
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Apr 12 03:29:58 2024 -0400
Simplify converting between SImode and SF/DFmode.
2024-04-12 Michael Meissner <meiss...@linux.ibm.com>
gcc/
PR target/90822
* gcc/config/rs6000.md (floatsidf2): If SImode can live in the
floating
point registers, directly issue a conversion to DImode and do the
floating point conversion.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
(floatsisf2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.md | 44 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f1f120199f3..32b0fd056fa 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,6 +6041,10 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6054,7 +6058,13 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], false);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6110,6 +6120,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6120,7 +6134,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdisf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6145,7 +6165,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6905,6 +6931,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6915,7 +6945,13 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], false);
+ emit_insn (gen_floatdisf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
