https://gcc.gnu.org/g:d97e784f9887aece6d857e5790ea931ea6e044ee
commit d97e784f9887aece6d857e5790ea931ea6e044ee
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Apr 12 03:25:09 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/rs6000.md | 44 ++++----------------------------------------
1 file changed, 4 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 251b5c486b0..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,10 +6041,6 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6058,13 +6054,7 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6120,10 +6110,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6134,13 +6120,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6165,13 +6145,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatunsdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6931,10 +6905,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6945,13 +6915,7 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
