https://gcc.gnu.org/g:0296376c2c19ba06eef70e36bbc41f5cfe947905
commit 0296376c2c19ba06eef70e36bbc41f5cfe947905 Author: Michael Meissner <meiss...@linux.ibm.com> Date: Fri Mar 8 16:42:18 2024 -0500 Add -mcpu=power11 support. This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. 2024-03-08 Michael Meissner <meiss...@linux.ibm.com> gcc/ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11 isa bit. (power11 cpu): Add power11 definition. * rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (power11_cost): Add power11 support. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. Diff: --- gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 ++++ gcc/config/rs6000/rs6000-opts.h | 3 ++- gcc/config/rs6000/rs6000-string.cc | 1 + gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.cc | 50 ++++++++++++++++++++++++++++++++----- gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 3 +++ gcc/doc/invoke.texi | 5 ++-- 9 files changed, 64 insertions(+), 10 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index ce0b14a8d37..ebed8b9554a 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); + if ((flags & OPTION_MASK_POWER11) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 28249600318..3237a5ada30 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,9 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) +#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_POWER11) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -125,6 +128,7 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ + | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ @@ -257,3 +261,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 33fd0efc936..4f5af57ae1a 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,7 +67,8 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN + PROCESSOR_TITAN, + PROCESSOR_POWER11 }; diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 917f5572a6d..9c8a81172e3 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -964,6 +964,7 @@ expand_compare_loop (rtx operands[]) break; case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (bytes_is_const) max_bytes = 191; else diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 65f46709716..7e5bb6e7658 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +EnumValue +Enum(rs6000_cpu_opt_value) String(power11) Value(57) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 6ba9df4f02e..5380dce7a07 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1087,6 +1087,26 @@ struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* SF->DF convert */ }; +/* Instruction costs on POWER11 processors. */ +static const +struct processor_costs power11_cost = { + COSTS_N_INSNS (2), /* mulsi */ + COSTS_N_INSNS (2), /* mulsi_const */ + COSTS_N_INSNS (2), /* mulsi_const9 */ + COSTS_N_INSNS (2), /* muldi */ + COSTS_N_INSNS (6), /* divsi */ + COSTS_N_INSNS (6), /* divdi */ + COSTS_N_INSNS (2), /* fp */ + COSTS_N_INSNS (2), /* dmul */ + COSTS_N_INSNS (11), /* sdiv */ + COSTS_N_INSNS (13), /* ddiv */ + 128, /* cache line size */ + 32, /* l1 cache */ + 512, /* l2 cache */ + 16, /* prefetch streams */ + COSTS_N_INSNS (2), /* SF->DF convert */ +}; + /* Instruction costs on POWER A2 processors. */ static const struct processor_costs ppca2_cost = { @@ -4379,7 +4399,8 @@ rs6000_option_override_internal (bool global_init_p) generating power10 instructions. */ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { - if (rs6000_tune == PROCESSOR_POWER10) + if (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4408,6 +4429,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 + && rs6000_tune != PROCESSOR_POWER11 && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4422,6 +4444,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4724,6 +4747,10 @@ rs6000_option_override_internal (bool global_init_p) rs6000_cost = &power10_cost; break; + case PROCESSOR_POWER11: + rs6000_cost = &power11_cost; + break; + case PROCESSOR_PPCA2: rs6000_cost = &ppca2_cost; break; @@ -5880,6 +5907,8 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); + if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) + return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -10126,6 +10155,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18207,7 +18237,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18246,6 +18277,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18820,6 +18852,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: + case PROCESSOR_POWER11: return 8; default: return 1; @@ -19536,7 +19569,9 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, load_store_pendulum = 0; /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19560,8 +19595,9 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22778,7 +22814,8 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24437,6 +24474,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, + { "power11", OPTION_MASK_POWER11, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bc8bc6ab060..ea4add5b283 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -351,7 +351,7 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan" + rs64a,mpccore,cell,ppca2,titan,power11" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 83197681b66..e7a4e4a2ddd 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -581,6 +581,9 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save mpower10 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved +mpower11 +Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>) + mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2390d478121..162e63cd149 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31153,8 +31153,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, and @samp{native}. +@samp{power9}, @samp{power10}, @samp{power11}, +@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, +@samp{rs64}, @samp{future}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either