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The branch, master has been updated via 7fae909b4b7f24a68c7f8bf019b4368e7a45cd1e (commit) from 07648bff40636f485254e27ccb2919dff1714fdf (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 7fae909b4b7f24a68c7f8bf019b4368e7a45cd1e Author: Haochen Jiang <haochen.ji...@intel.com> Date: Fri Jun 13 11:09:28 2025 +0800 gcc-15: Correct DMR ISA base platform to include AMX-COMPLEX diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index 5d35253a..d0b289e1 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs/gcc-15/changes.html @@ -1227,10 +1227,10 @@ structure used in <code>core 1.49</code>. </li> <li>GCC now supports the Intel CPU named Diamond Rapids through <code>-march=diamondrapids</code>. - Based on Granite Rapids, the switch further enables the AMX-AVX512, - AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2, AVX-IFMA, - AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, MOVRS, SHA512, - SM3, SM4, and USER_MSR ISA extensions. + Based on ISA extensions enabled on Granite Rapids D, the switch further + enables the AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, + AVX10.2, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, + CMPccXADD, MOVRS, SHA512, SM3, SM4, and USER_MSR ISA extensions. </li> <li>Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were removed in GCC 15. GCC will no longer accept <code>-march=knl</code>, ----------------------------------------------------------------------- Summary of changes: htdocs/gcc-15/changes.html | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) hooks/post-receive -- gcc-wwwdocs