[Bug target/19556] [4.0 Regression] ICE with -march=pentium-m (during bootstrap)

[steven at gcc dot gnu dot org]

------- Additional Comments From steven at gcc dot gnu dot org  2005-01-21 
11:38 -------
Looks like a reload problem (of course). 
 
In the .lreg dump we have this: 
 
(insn:HI 100 99 101 9 (set (reg/v/f:SI 64 [ all_ovr_obj ]) 
        (reg/f:SI 87)) 41 {*movsi_1} (nil) 
    (nil)) 
 
 
In the .greg dump we get these reloads for insn 100: 
 
Spilling for insn 100. 
... 
Spilling for insn 100. 
... 
Reloads for insn # 100 
Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 6 bp) 
                                                    (const_int -28 
[0xffffffffffffffe4])) 
        SSE_REGS, RELOAD_FOR_INPUT (opnum = 1) 
        reload_in_reg: (plus:SI (reg/f:SI 6 bp) 
                                                    (const_int -28 
[0xffffffffffffffe4])) 
        reload_reg_rtx: (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) 
... 
 
At the moment of the ICE we have this: 
 
(insn 287 99 288 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) 
        (reg/f:SI 6 bp)) 41 {*movsi_1} (nil) 
    (nil)) 
 
(insn 288 287 100 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) 
        (plus:SI (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) 
            (const_int -28 [0xffffffffffffffe4]))) -1 (nil) 
    (expr_list:REG_EQUIV (plus:SI (reg/f:SI 6 bp) 
            (const_int -28 [0xffffffffffffffe4])) 
        (nil))) 
 
(insn:HI 100 288 101 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) 
        (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64])) 41 {*movsi_1} (nil) 
    (nil)) 
 
Why does reload reload an SImode register to an sse register? 
 

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19556