[Bug target/127374] New: Zicond improvement for RISC-V

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127374

            Bug ID: 127374
           Summary: Zicond improvement for RISC-V
           Product: gcc
           Version: 17.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: law at gcc dot gnu.org
  Target Milestone: ---

bool f2(int x)
{
    if ((unsigned)x > 15)
        return false;

    return (x & 1) == 0;
}



With -O2 -march=rv64gcbv_zicond will eventually try this combination:

Trying 7, 35 -> 36:
    7: r138:DI=0xf
   35: r146:DI=gtu(r137:DI,r138:DI)
      REG_DEAD r138:DI
      REG_DEAD r137:DI
   36: r148:DI={(r146:DI!=0)?0:r145:DI}
      REG_DEAD r146:DI
      REG_DEAD r145:DI
Failed to match this instruction:
(set (reg:DI 148)
    (if_then_else:DI (leu:DI (reg/v:DI 137 [ x ])
            (const_int 15 [0xf]))
        (reg:DI 145)
        (const_int 0 [0])))


That's sltiu+czero I think, a simple 3->2 split.