[Bug rtl-optimization/127367] [17 Regression] RISC-V: wrong code for unsigned _BitInt(96) %

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127367

Drea Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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           Keywords|                            |needs-bisection

--- Comment #1 from Drea Pinski <pinskia at gcc dot gnu.org> ---
x86_64 works and the gimple level looks the same between riscv and x86_64 so
most likely a rtl or a rtl issue.