https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127362
Bug ID: 127362
Summary: More masking cases that can be improved on RISC-V
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
Consider:
(set (reg:DI 174)
(and:DI (not:DI (reg:DI 183))
(const_int -9223372036854775808 [0x8000000000000000])))
That's just bseti + andn on RISC-V.
More generally, any constant that can be synthesized in a single instruction
works. It also generalizes to the xor and ior I suspect.
