[Bug target/125994] New: riscv: Vector misalignment hook doesn't handle scalar modes.

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125994

            Bug ID: 125994
           Summary: riscv: Vector misalignment hook doesn't handle scalar
                    modes.
           Product: gcc
           Version: 17.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rdapp at gcc dot gnu.org
  Target Milestone: ---
            Target: riscv

Julien Thillard reported off list to me that we're not peeling for alignment
anymore in the following function:

#include <stdint.h>

void
AddWithIv (uint8_t *restrict buf, uint8_t *restrict Iv, uint64_t size)
{
  uint64_t i;
  for (i = 0; i < size; ++i)
    {
      buf[i] += Iv[i];
    }
}

Instead, we get a potentially misaligned scalar access that we split into byte
accesses at expand on slow-misalign targets (currently the default).
This means that with e.g. -march=rv64gc -O3 we get byte accesses in the loop
instead of "SWAR" loads.

Thanks Julien for reporting this and tracking down the (my :)) offending
commit.

I have a patch.